206 lines
6.4 KiB
Verilog
206 lines
6.4 KiB
Verilog
`include "VX_define.vh"
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module VX_gpu_unit #(
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parameter CORE_ID = 0
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) (
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`SCOPE_IO_VX_gpu_unit
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input wire clk,
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input wire reset,
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// Inputs
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VX_gpu_req_if gpu_req_if,
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`ifdef EXT_TEX_ENABLE
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VX_tex_csr_if tex_csr_if,
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VX_dcache_req_if dcache_req_if,
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VX_dcache_rsp_if dcache_rsp_if,
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`endif
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// Outputs
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VX_warp_ctl_if warp_ctl_if,
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VX_commit_if gpu_commit_if
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);
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`UNUSED_PARAM (CORE_ID)
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wire rsp_valid;
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wire [`NW_BITS-1:0] rsp_wid;
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wire [`NUM_THREADS-1:0] rsp_tmask;
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wire [31:0] rsp_PC;
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wire [`NR_BITS-1:0] rsp_rd;
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wire rsp_wb;
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wire [`NUM_THREADS-1:0][31:0] rsp_data;
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gpu_tmc_t tmc;
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gpu_wspawn_t wspawn;
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gpu_barrier_t barrier;
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gpu_split_t split;
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wire [(`NUM_THREADS * 32)-1:0] warp_ctl_data;
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wire is_warp_ctl;
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wire stall_in, stall_out;
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wire is_wspawn = (gpu_req_if.op_type == `GPU_WSPAWN);
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wire is_tmc = (gpu_req_if.op_type == `GPU_TMC);
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wire is_split = (gpu_req_if.op_type == `GPU_SPLIT);
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wire is_bar = (gpu_req_if.op_type == `GPU_BAR);
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// tmc
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wire [`NUM_THREADS-1:0] tmc_new_mask;
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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assign tmc_new_mask[i] = (i < gpu_req_if.rs1_data[0]);
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end
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assign tmc.valid = is_tmc;
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assign tmc.tmask = tmc_new_mask;
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// wspawn
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wire [31:0] wspawn_pc = gpu_req_if.rs2_data[0];
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wire [`NUM_WARPS-1:0] wspawn_wmask;
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for (genvar i = 0; i < `NUM_WARPS; i++) begin
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assign wspawn_wmask[i] = (i < gpu_req_if.rs1_data[0]);
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end
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assign wspawn.valid = is_wspawn;
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assign wspawn.wmask = wspawn_wmask;
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assign wspawn.pc = wspawn_pc;
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// split
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wire [`NUM_THREADS-1:0] split_then_mask;
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wire [`NUM_THREADS-1:0] split_else_mask;
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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wire taken = gpu_req_if.rs1_data[i][0];
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assign split_then_mask[i] = gpu_req_if.tmask[i] & taken;
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assign split_else_mask[i] = gpu_req_if.tmask[i] & ~taken;
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end
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assign split.valid = is_split;
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assign split.diverged = (| split_then_mask) && (| split_else_mask);
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assign split.then_mask = split_then_mask;
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assign split.else_mask = split_else_mask;
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assign split.pc = gpu_req_if.next_PC;
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// barrier
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assign barrier.valid = is_bar;
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assign barrier.id = gpu_req_if.rs1_data[0][`NB_BITS-1:0];
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assign barrier.size_m1 = (`NW_BITS)'(gpu_req_if.rs2_data[0] - 1);
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// pack warp ctl result
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`IGNORE_WARNINGS_BEGIN
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assign warp_ctl_data = {tmc, wspawn, barrier, split};
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`IGNORE_WARNINGS_END
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// texture
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`ifdef EXT_TEX_ENABLE
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`UNUSED_VAR (gpu_req_if.op_mod)
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VX_tex_req_if tex_req_if();
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VX_tex_rsp_if tex_rsp_if();
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wire is_tex = (gpu_req_if.op_type == `GPU_TEX);
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assign tex_req_if.valid = gpu_req_if.valid && is_tex;
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assign tex_req_if.wid = gpu_req_if.wid;
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assign tex_req_if.tmask = gpu_req_if.tmask;
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assign tex_req_if.PC = gpu_req_if.PC;
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assign tex_req_if.rd = gpu_req_if.rd;
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assign tex_req_if.wb = gpu_req_if.wb;
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assign tex_req_if.unit = gpu_req_if.op_mod[`NTEX_BITS-1:0];
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assign tex_req_if.coords[0] = gpu_req_if.rs1_data;
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assign tex_req_if.coords[1] = gpu_req_if.rs2_data;
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assign tex_req_if.lod = gpu_req_if.rs3_data;
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VX_tex_unit #(
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.CORE_ID(CORE_ID)
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) tex_unit (
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.clk (clk),
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.reset (reset),
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.tex_req_if (tex_req_if),
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.tex_csr_if (tex_csr_if),
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.tex_rsp_if (tex_rsp_if),
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.dcache_req_if (dcache_req_if),
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.dcache_rsp_if (dcache_rsp_if)
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);
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assign tex_rsp_if.ready = !stall_out;
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assign stall_in = (is_tex && ~tex_req_if.ready)
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|| (~is_tex && (tex_rsp_if.valid || stall_out));
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assign is_warp_ctl = !(is_tex || tex_rsp_if.valid);
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assign rsp_valid = tex_rsp_if.valid || (gpu_req_if.valid && ~is_tex);
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assign rsp_wid = tex_rsp_if.valid ? tex_rsp_if.wid : gpu_req_if.wid;
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assign rsp_tmask = tex_rsp_if.valid ? tex_rsp_if.tmask : gpu_req_if.tmask;
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assign rsp_PC = tex_rsp_if.valid ? tex_rsp_if.PC : gpu_req_if.PC;
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assign rsp_rd = tex_rsp_if.rd;
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assign rsp_wb = tex_rsp_if.valid && tex_rsp_if.wb;
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assign rsp_data = tex_rsp_if.valid ? tex_rsp_if.data : warp_ctl_data;
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`else
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`UNUSED_VAR (gpu_req_if.op_mod)
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`UNUSED_VAR (gpu_req_if.rs2_data)
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`UNUSED_VAR (gpu_req_if.rs3_data)
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`UNUSED_VAR (gpu_req_if.wb)
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`UNUSED_VAR (gpu_req_if.rd)
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assign stall_in = stall_out;
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assign is_warp_ctl = 1;
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assign rsp_valid = gpu_req_if.valid;
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assign rsp_wid = gpu_req_if.wid;
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assign rsp_tmask = gpu_req_if.tmask;
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assign rsp_PC = gpu_req_if.PC;
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assign rsp_rd = 0;
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assign rsp_wb = 0;
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assign rsp_data = warp_ctl_data;
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`endif
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wire is_warp_ctl_r;
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// output
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assign stall_out = ~gpu_commit_if.ready && gpu_commit_if.valid;
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VX_pipe_register #(
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.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1),
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.RESETW (1)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (!stall_out),
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.data_in ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, rsp_data, is_warp_ctl}),
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.data_out ({gpu_commit_if.valid, gpu_commit_if.wid, gpu_commit_if.tmask, gpu_commit_if.PC, gpu_commit_if.rd, gpu_commit_if.wb, gpu_commit_if.data, is_warp_ctl_r})
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);
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assign gpu_commit_if.eop = 1'b1;
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// warp control reponse
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`IGNORE_WARNINGS_BEGIN
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assign {warp_ctl_if.tmc, warp_ctl_if.wspawn, warp_ctl_if.barrier, warp_ctl_if.split} = gpu_commit_if.data;
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`IGNORE_WARNINGS_END
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assign warp_ctl_if.valid = gpu_commit_if.valid && gpu_commit_if.ready && is_warp_ctl_r;
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assign warp_ctl_if.wid = gpu_commit_if.wid;
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// can accept new request?
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assign gpu_req_if.ready = ~stall_in;
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`SCOPE_ASSIGN (gpu_rsp_valid, warp_ctl_if.valid);
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`SCOPE_ASSIGN (gpu_rsp_wid, warp_ctl_if.wid);
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`SCOPE_ASSIGN (gpu_rsp_tmc, warp_ctl_if.tmc);
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`SCOPE_ASSIGN (gpu_rsp_wspawn, warp_ctl_if.wspawn);
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`SCOPE_ASSIGN (gpu_rsp_split, warp_ctl_if.split);
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`SCOPE_ASSIGN (gpu_rsp_barrier, warp_ctl_if.barrier);
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endmodule |