Commit Graph

26 Commits

Author SHA1 Message Date
Blaise Tine
bb1ceffadd rebase master update 2021-07-30 21:03:14 -07:00
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062d02ddce Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2021-03-04 20:51:03 -08:00
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9f128085d5 scoreboard optimization - using writeback's end-of-packet status 2020-12-30 06:47:56 -08:00
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d44144f72f FPU float<->int conversion optimization 2020-12-29 15:37:45 -08:00
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4bbd7bf408 performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies, 2020-12-19 02:45:06 -08:00
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13a5370254 register file refactoring 2020-12-05 01:40:50 -08:00
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5758ef9ebf generic_register reset network optimization 2020-11-29 18:41:36 -08:00
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461be0880d fixed FPU-CSR data dependence 2020-11-25 09:05:38 -08:00
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34b650be94 fixed shared memory addressing critical path, fixed VX_fp_noncomp output bug 2020-11-17 00:27:24 -08:00
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10505caae1 refactoring all arbiters with buffering for request count > 2, optimized the cache core response module in critical path when running as L2 2020-11-08 01:31:46 -08:00
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5be1d85648 cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count 2020-11-02 01:50:12 -08:00
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9a9f7955f0 basic test timing + scope tracing ccip 2020-10-27 17:04:04 -04:00
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32da50816f scope refactoring: adding modules definitions to VCD trace 2020-10-12 23:26:02 -04:00
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49b86c4b2a SCOPE update 2020-09-05 10:52:59 -07:00
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b211b29670 removing pipeline additional registers 2020-08-25 14:02:35 -07:00
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57971f6c76 decode op_mod optimization 2020-08-24 02:55:14 -07:00
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f292e5003d quartus build fixes 2020-08-23 22:04:46 -07:00
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0b355f228e ibuffer addition 2020-08-22 00:22:04 -07:00
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6c12391338 pipeline refactoring - fmax >= 222 mhz 2020-08-14 21:50:14 -07:00
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27e95530ef pipeline optimization 2020-07-30 03:06:01 -07:00
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8976100025 floating point support fixes 2020-07-28 04:19:46 -04:00
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7c86b68977 pipeline refactoring: centralized issue buffer 2020-07-26 11:21:08 -04:00
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75e3c31b56 fpu implementation (part1) 2020-07-23 03:18:09 -07:00
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dc7efbcfb4 pipeline refactoring 2020-07-21 05:22:47 -04:00
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577a5791dc pipeline refactoring 2020-07-20 08:04:04 -04:00
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25f66e6490 pipeline refactoring 2020-07-19 05:03:47 -04:00