Blaise Tine b85391389b rename MSRQ to MSHR

2020-11-28 17:32:00 -05:00

..

VX_bank_core_req_arb.v

reset networks optimization

2020-11-16 01:12:02 -08:00

VX_bank.v

rename MSRQ to MSHR

2020-11-28 17:32:00 -05:00

VX_cache_config.vh

rename MSRQ to MSHR

2020-11-28 17:32:00 -05:00

VX_cache_core_req_bank_sel.v

L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization

2020-11-21 09:47:56 -08:00

VX_cache_core_rsp_merge.v

fixed shared memory addressing critical path, fixed VX_fp_noncomp output bug

2020-11-17 00:27:24 -08:00

VX_cache_dram_req_arb.v

refactoring all arbiters with buffering for request count > 2, optimized the cache core response module in critical path when running as L2

2020-11-08 01:31:46 -08:00

VX_cache_miss_resrv.v

rename MSRQ to MSHR

2020-11-28 17:32:00 -05:00

VX_cache.v

rename MSRQ to MSHR

2020-11-28 17:32:00 -05:00

VX_data_access.v

fixed shared memory addressing critical path, fixed VX_fp_noncomp output bug

2020-11-17 00:27:24 -08:00

VX_data_store.v

tabs cleanup

2020-11-28 17:08:01 -05:00

VX_snp_forwarder.v

scope minor fix

2020-11-22 11:51:46 -08:00

VX_snp_rsp_arb.v

L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization

2020-11-21 09:47:56 -08:00

VX_tag_access.v

minor update

2020-11-28 03:22:11 -05:00

VX_tag_store.v

tabs cleanup

2020-11-28 17:08:01 -05:00