460 lines
20 KiB
Verilog
460 lines
20 KiB
Verilog
`include "VX_cache_define.vh"
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module VX_cache #(
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parameter CACHE_ID = 0,
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// Number of Word requests per cycle
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parameter NUM_REQS = 4,
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// Size of cache in bytes
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parameter CACHE_SIZE = 16384,
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// Size of line inside a bank in bytes
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parameter CACHE_LINE_SIZE = 64,
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// Number of banks
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parameter NUM_BANKS = NUM_REQS,
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// Number of ports per banks
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parameter NUM_PORTS = 1,
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// Size of a word in bytes
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parameter WORD_SIZE = 4,
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// Core Request Queue Size
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parameter CREQ_SIZE = 4,
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// Miss Reserv Queue Knob
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parameter MSHR_SIZE = 8,
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// Memory Response Queue Size
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parameter MRSQ_SIZE = 4,
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// Memory Request Queue Size
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parameter MREQ_SIZE = 4,
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// Enable cache writeable
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parameter WRITE_ENABLE = 1,
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// core request tag size
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parameter CORE_TAG_WIDTH = $clog2(MSHR_SIZE),
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// size of tag id in core request tag
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parameter CORE_TAG_ID_BITS = CORE_TAG_WIDTH,
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// Memory request tag size
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parameter MEM_TAG_WIDTH = (32 - $clog2(CACHE_LINE_SIZE)),
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// bank offset from beginning of index range
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parameter BANK_ADDR_OFFSET = 0
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) (
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`SCOPE_IO_VX_cache
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input wire clk,
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input wire reset,
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// Core request
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input wire [NUM_REQS-1:0] core_req_valid,
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input wire [NUM_REQS-1:0] core_req_rw,
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input wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr,
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input wire [NUM_REQS-1:0][WORD_SIZE-1:0] core_req_byteen,
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input wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_req_data,
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input wire [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
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output wire [NUM_REQS-1:0] core_req_ready,
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// Core response
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output wire [NUM_REQS-1:0] core_rsp_valid,
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output wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data,
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output wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag,
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input wire [`CORE_REQ_TAG_COUNT-1:0] core_rsp_ready,
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// Memory request
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output wire mem_req_valid,
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output wire mem_req_rw,
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output wire [CACHE_LINE_SIZE-1:0] mem_req_byteen,
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output wire [`MEM_ADDR_WIDTH-1:0] mem_req_addr,
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output wire [`CACHE_LINE_WIDTH-1:0] mem_req_data,
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output wire [MEM_TAG_WIDTH-1:0] mem_req_tag,
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input wire mem_req_ready,
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// Memory response
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input wire mem_rsp_valid,
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input wire [`CACHE_LINE_WIDTH-1:0] mem_rsp_data,
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input wire [MEM_TAG_WIDTH-1:0] mem_rsp_tag,
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output wire mem_rsp_ready,
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// PERF
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`ifdef PERF_ENABLE
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VX_perf_cache_if perf_cache_if,
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`endif
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// device flush
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input wire flush
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);
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`STATIC_ASSERT(NUM_BANKS <= NUM_REQS, ("invalid value"))
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wire [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_req_valid;
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wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`UP(`WORD_SELECT_BITS)-1:0] per_bank_core_req_wsel;
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wire [NUM_BANKS-1:0][NUM_PORTS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen;
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wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data;
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wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid;
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wire [NUM_BANKS-1:0] per_bank_core_req_rw;
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wire [NUM_BANKS-1:0][`LINE_ADDR_WIDTH-1:0] per_bank_core_req_addr;
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wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag;
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wire [NUM_BANKS-1:0] per_bank_core_req_ready;
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wire [NUM_BANKS-1:0] per_bank_core_rsp_valid;
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wire [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_rsp_pmask;
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wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`WORD_WIDTH-1:0] per_bank_core_rsp_data;
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wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`REQS_BITS-1:0] per_bank_core_rsp_tid;
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wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_rsp_tag;
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wire [NUM_BANKS-1:0] per_bank_core_rsp_ready;
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wire [NUM_BANKS-1:0] per_bank_mem_req_valid;
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wire [NUM_BANKS-1:0] per_bank_mem_req_rw;
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wire [NUM_BANKS-1:0][CACHE_LINE_SIZE-1:0] per_bank_mem_req_byteen;
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wire [NUM_BANKS-1:0][`MEM_ADDR_WIDTH-1:0] per_bank_mem_req_addr;
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wire [NUM_BANKS-1:0][`CACHE_LINE_WIDTH-1:0] per_bank_mem_req_data;
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wire [NUM_BANKS-1:0] per_bank_mem_req_ready;
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wire [NUM_BANKS-1:0] per_bank_mem_rsp_ready;
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wire [`CACHE_LINE_WIDTH-1:0] mem_rsp_data_qual;
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wire [MEM_TAG_WIDTH-1:0] mem_rsp_tag_qual;
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wire [`LINE_SELECT_BITS-1:0] flush_addr;
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wire flush_enable;
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`ifdef PERF_ENABLE
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wire [NUM_BANKS-1:0] perf_read_miss_per_bank;
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wire [NUM_BANKS-1:0] perf_write_miss_per_bank;
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wire [NUM_BANKS-1:0] perf_mshr_stall_per_bank;
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wire [NUM_BANKS-1:0] perf_pipe_stall_per_bank;
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`endif
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///////////////////////////////////////////////////////////////////////////
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wire mrsq_full, mrsq_empty;
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wire mrsq_push, mrsq_pop;
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assign mrsq_push = mem_rsp_valid && mem_rsp_ready;
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assign mem_rsp_ready = !mrsq_full;
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VX_fifo_queue #(
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.DATAW (MEM_TAG_WIDTH + `CACHE_LINE_WIDTH),
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.SIZE (MRSQ_SIZE),
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.BUFFERED (1)
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) mem_rsp_queue (
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.clk (clk),
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.reset (reset),
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.push (mrsq_push),
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.pop (mrsq_pop),
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.data_in ({mem_rsp_tag, mem_rsp_data}),
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.data_out ({mem_rsp_tag_qual, mem_rsp_data_qual}),
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.empty (mrsq_empty),
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.full (mrsq_full),
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`UNUSED_PIN (alm_full),
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`UNUSED_PIN (alm_empty),
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`UNUSED_PIN (size)
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);
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if (NUM_BANKS == 1) begin
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`UNUSED_VAR (mem_rsp_tag_qual)
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assign mrsq_pop = !mrsq_empty && per_bank_mem_rsp_ready;
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end else begin
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assign mrsq_pop = !mrsq_empty && per_bank_mem_rsp_ready[`MEM_ADDR_BANK(mem_rsp_tag_qual)];
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end
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///////////////////////////////////////////////////////////////////////////
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VX_flush_ctrl #(
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.CACHE_SIZE (CACHE_SIZE),
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.CACHE_LINE_SIZE (CACHE_LINE_SIZE),
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.NUM_BANKS (NUM_BANKS)
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) flush_ctrl (
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.clk (clk),
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.reset (reset || flush),
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.addr_out (flush_addr),
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.valid_out (flush_enable)
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);
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///////////////////////////////////////////////////////////////////////////
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VX_cache_core_req_bank_sel #(
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.CACHE_ID (CACHE_ID),
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.CACHE_LINE_SIZE (CACHE_LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.NUM_PORTS (NUM_PORTS),
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.WORD_SIZE (WORD_SIZE),
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.NUM_REQS (NUM_REQS),
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.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
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.BANK_ADDR_OFFSET(BANK_ADDR_OFFSET)
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) core_req_bank_sel (
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.clk (clk),
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.reset (reset),
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`ifdef PERF_ENABLE
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.bank_stalls(perf_cache_if.bank_stalls),
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`endif
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.core_req_valid (core_req_valid),
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.core_req_rw (core_req_rw),
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.core_req_addr (core_req_addr),
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.core_req_byteen(core_req_byteen),
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.core_req_data (core_req_data),
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.core_req_tag (core_req_tag),
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.core_req_ready (core_req_ready),
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.per_bank_core_req_valid (per_bank_core_req_valid),
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.per_bank_core_req_rw (per_bank_core_req_rw),
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.per_bank_core_req_addr (per_bank_core_req_addr),
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.per_bank_core_req_wsel (per_bank_core_req_wsel),
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.per_bank_core_req_byteen(per_bank_core_req_byteen),
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.per_bank_core_req_data (per_bank_core_req_data),
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.per_bank_core_req_tag (per_bank_core_req_tag),
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.per_bank_core_req_tid (per_bank_core_req_tid),
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.per_bank_core_req_ready (per_bank_core_req_ready)
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);
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///////////////////////////////////////////////////////////////////////////
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for (genvar i = 0; i < NUM_BANKS; i++) begin
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wire [NUM_PORTS-1:0] curr_bank_core_req_valid;
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wire [NUM_PORTS-1:0][`UP(`WORD_SELECT_BITS)-1:0] curr_bank_core_req_wsel;
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wire [NUM_PORTS-1:0][WORD_SIZE-1:0] curr_bank_core_req_byteen;
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wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] curr_bank_core_req_data;
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wire [NUM_PORTS-1:0][`REQS_BITS-1:0] curr_bank_core_req_tid;
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wire curr_bank_core_req_rw;
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wire [`LINE_ADDR_WIDTH-1:0] curr_bank_core_req_addr;
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wire [CORE_TAG_WIDTH-1:0] curr_bank_core_req_tag;
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wire curr_bank_core_req_ready;
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wire curr_bank_core_rsp_valid;
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wire [NUM_PORTS-1:0] curr_bank_core_rsp_pmask;
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wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] curr_bank_core_rsp_data;
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wire [NUM_PORTS-1:0][`REQS_BITS-1:0] curr_bank_core_rsp_tid;
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wire [CORE_TAG_WIDTH-1:0] curr_bank_core_rsp_tag;
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wire curr_bank_core_rsp_ready;
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wire curr_bank_mem_req_valid;
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wire curr_bank_mem_req_rw;
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wire [CACHE_LINE_SIZE-1:0] curr_bank_mem_req_byteen;
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wire [`LINE_ADDR_WIDTH-1:0] curr_bank_mem_req_addr;
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wire[`CACHE_LINE_WIDTH-1:0] curr_bank_mem_req_data;
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wire curr_bank_mem_req_ready;
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wire curr_bank_mem_rsp_valid;
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wire [`LINE_ADDR_WIDTH-1:0] curr_bank_mem_rsp_addr;
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wire [`CACHE_LINE_WIDTH-1:0] curr_bank_mem_rsp_data;
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wire curr_bank_mem_rsp_ready;
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// Core Req
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assign curr_bank_core_req_valid = per_bank_core_req_valid[i];
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assign curr_bank_core_req_addr = per_bank_core_req_addr[i];
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assign curr_bank_core_req_rw = per_bank_core_req_rw[i];
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assign curr_bank_core_req_wsel = per_bank_core_req_wsel[i];
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assign curr_bank_core_req_byteen = per_bank_core_req_byteen[i];
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assign curr_bank_core_req_data = per_bank_core_req_data[i];
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assign curr_bank_core_req_tag = per_bank_core_req_tag[i];
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assign curr_bank_core_req_tid = per_bank_core_req_tid[i];
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assign per_bank_core_req_ready[i] = curr_bank_core_req_ready;
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// Core WB
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assign curr_bank_core_rsp_ready = per_bank_core_rsp_ready[i];
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assign per_bank_core_rsp_valid[i] = curr_bank_core_rsp_valid;
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assign per_bank_core_rsp_pmask[i] = curr_bank_core_rsp_pmask;
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assign per_bank_core_rsp_tid [i] = curr_bank_core_rsp_tid;
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assign per_bank_core_rsp_tag [i] = curr_bank_core_rsp_tag;
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assign per_bank_core_rsp_data [i] = curr_bank_core_rsp_data;
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// Memory request
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assign per_bank_mem_req_valid[i] = curr_bank_mem_req_valid;
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assign per_bank_mem_req_rw[i] = curr_bank_mem_req_rw;
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assign per_bank_mem_req_byteen[i] = curr_bank_mem_req_byteen;
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if (NUM_BANKS == 1) begin
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assign per_bank_mem_req_addr[i] = curr_bank_mem_req_addr;
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end else begin
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assign per_bank_mem_req_addr[i] = `LINE_TO_MEM_ADDR(curr_bank_mem_req_addr, i);
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end
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assign per_bank_mem_req_data[i] = curr_bank_mem_req_data;
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assign curr_bank_mem_req_ready = per_bank_mem_req_ready[i];
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// Memory response
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if (NUM_BANKS == 1) begin
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assign curr_bank_mem_rsp_valid = !mrsq_empty;
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assign curr_bank_mem_rsp_addr = mem_rsp_tag_qual;
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end else begin
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assign curr_bank_mem_rsp_valid = !mrsq_empty && (`MEM_ADDR_BANK(mem_rsp_tag_qual) == i);
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assign curr_bank_mem_rsp_addr = `MEM_TO_LINE_ADDR(mem_rsp_tag_qual);
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end
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assign curr_bank_mem_rsp_data = mem_rsp_data_qual;
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assign per_bank_mem_rsp_ready[i] = curr_bank_mem_rsp_ready;
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VX_bank #(
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.BANK_ID (i),
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.CACHE_ID (CACHE_ID),
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.CACHE_SIZE (CACHE_SIZE),
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.CACHE_LINE_SIZE (CACHE_LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.NUM_PORTS (NUM_PORTS),
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.WORD_SIZE (WORD_SIZE),
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.NUM_REQS (NUM_REQS),
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.CREQ_SIZE (CREQ_SIZE),
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.MSHR_SIZE (MSHR_SIZE),
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.MREQ_SIZE (MREQ_SIZE),
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.WRITE_ENABLE (WRITE_ENABLE),
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.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS),
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.BANK_ADDR_OFFSET (BANK_ADDR_OFFSET)
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) bank (
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`SCOPE_BIND_VX_cache_bank(i)
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.clk (clk),
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.reset (reset),
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`ifdef PERF_ENABLE
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.perf_read_misses (perf_read_miss_per_bank[i]),
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.perf_write_misses (perf_write_miss_per_bank[i]),
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.perf_mshr_stalls (perf_mshr_stall_per_bank[i]),
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.perf_pipe_stalls (perf_pipe_stall_per_bank[i]),
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`endif
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// Core request
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.core_req_valid (curr_bank_core_req_valid),
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.core_req_rw (curr_bank_core_req_rw),
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.core_req_byteen (curr_bank_core_req_byteen),
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.core_req_addr (curr_bank_core_req_addr),
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.core_req_wsel (curr_bank_core_req_wsel),
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.core_req_data (curr_bank_core_req_data),
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.core_req_tag (curr_bank_core_req_tag),
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.core_req_tid (curr_bank_core_req_tid),
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.core_req_ready (curr_bank_core_req_ready),
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// Core response
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.core_rsp_valid (curr_bank_core_rsp_valid),
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.core_rsp_pmask (curr_bank_core_rsp_pmask),
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.core_rsp_tid (curr_bank_core_rsp_tid),
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.core_rsp_data (curr_bank_core_rsp_data),
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.core_rsp_tag (curr_bank_core_rsp_tag),
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.core_rsp_ready (curr_bank_core_rsp_ready),
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// Memory request
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.mem_req_valid (curr_bank_mem_req_valid),
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.mem_req_rw (curr_bank_mem_req_rw),
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.mem_req_byteen (curr_bank_mem_req_byteen),
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.mem_req_addr (curr_bank_mem_req_addr),
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.mem_req_data (curr_bank_mem_req_data),
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.mem_req_ready (curr_bank_mem_req_ready),
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// Memory response
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.mem_rsp_valid (curr_bank_mem_rsp_valid),
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.mem_rsp_addr (curr_bank_mem_rsp_addr),
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.mem_rsp_data (curr_bank_mem_rsp_data),
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.mem_rsp_ready (curr_bank_mem_rsp_ready),
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// flush
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.flush_enable (flush_enable),
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.flush_addr (flush_addr)
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);
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end
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VX_cache_core_rsp_merge #(
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.CACHE_ID (CACHE_ID),
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.NUM_BANKS (NUM_BANKS),
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.NUM_PORTS (NUM_PORTS),
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.WORD_SIZE (WORD_SIZE),
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.NUM_REQS (NUM_REQS),
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.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS)
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) core_rsp_merge (
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.clk (clk),
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.reset (reset),
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.per_bank_core_rsp_valid (per_bank_core_rsp_valid),
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.per_bank_core_rsp_pmask (per_bank_core_rsp_pmask),
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.per_bank_core_rsp_data (per_bank_core_rsp_data),
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.per_bank_core_rsp_tag (per_bank_core_rsp_tag),
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.per_bank_core_rsp_tid (per_bank_core_rsp_tid),
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.per_bank_core_rsp_ready (per_bank_core_rsp_ready),
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.core_rsp_valid (core_rsp_valid),
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.core_rsp_tag (core_rsp_tag),
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.core_rsp_data (core_rsp_data),
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.core_rsp_ready (core_rsp_ready)
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);
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wire [NUM_BANKS-1:0][(`MEM_ADDR_WIDTH + 1 + CACHE_LINE_SIZE + `CACHE_LINE_WIDTH)-1:0] data_in;
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for (genvar i = 0; i < NUM_BANKS; i++) begin
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assign data_in[i] = {per_bank_mem_req_addr[i], per_bank_mem_req_rw[i], per_bank_mem_req_byteen[i], per_bank_mem_req_data[i]};
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end
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VX_stream_arbiter #(
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.NUM_REQS (NUM_BANKS),
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.DATAW (`MEM_ADDR_WIDTH + 1 + CACHE_LINE_SIZE + `CACHE_LINE_WIDTH),
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.BUFFERED (1)
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) mem_req_arb (
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.clk (clk),
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.reset (reset),
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.valid_in (per_bank_mem_req_valid),
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.data_in (data_in),
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.ready_in (per_bank_mem_req_ready),
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.valid_out (mem_req_valid),
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|
.data_out ({mem_req_addr, mem_req_rw, mem_req_byteen, mem_req_data}),
|
|
.ready_out (mem_req_ready)
|
|
);
|
|
|
|
assign mem_req_tag = mem_req_addr;
|
|
|
|
`ifdef PERF_ENABLE
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|
// per cycle: core_reads, core_writes
|
|
reg [($clog2(NUM_REQS+1)-1):0] perf_core_reads_per_cycle;
|
|
reg [($clog2(NUM_REQS+1)-1):0] perf_core_writes_per_cycle;
|
|
reg [($clog2(NUM_REQS+1)-1):0] perf_crsp_stall_per_cycle;
|
|
|
|
assign perf_core_reads_per_cycle = $countones(core_req_valid & core_req_ready & ~core_req_rw);
|
|
assign perf_core_writes_per_cycle = $countones(core_req_valid & core_req_ready & core_req_rw);
|
|
|
|
if (CORE_TAG_ID_BITS != 0) begin
|
|
assign perf_crsp_stall_per_cycle = $countones(core_rsp_valid & {NUM_REQS{!core_rsp_ready}});
|
|
end else begin
|
|
assign perf_crsp_stall_per_cycle = $countones(core_rsp_valid & ~core_rsp_ready);
|
|
end
|
|
|
|
// per cycle: read misses, write misses, msrq stalls, pipeline stalls
|
|
reg [($clog2(NUM_BANKS+1)-1):0] perf_read_miss_per_cycle;
|
|
reg [($clog2(NUM_BANKS+1)-1):0] perf_write_miss_per_cycle;
|
|
reg [($clog2(NUM_BANKS+1)-1):0] perf_mshr_stall_per_cycle;
|
|
reg [($clog2(NUM_BANKS+1)-1):0] perf_pipe_stall_per_cycle;
|
|
|
|
assign perf_read_miss_per_cycle = $countones(perf_read_miss_per_bank);
|
|
assign perf_write_miss_per_cycle = $countones(perf_write_miss_per_bank);
|
|
assign perf_mshr_stall_per_cycle = $countones(perf_mshr_stall_per_bank);
|
|
assign perf_pipe_stall_per_cycle = $countones(perf_pipe_stall_per_bank);
|
|
|
|
reg [`PERF_CTR_BITS-1:0] perf_core_reads;
|
|
reg [`PERF_CTR_BITS-1:0] perf_core_writes;
|
|
reg [`PERF_CTR_BITS-1:0] perf_read_misses;
|
|
reg [`PERF_CTR_BITS-1:0] perf_write_misses;
|
|
reg [`PERF_CTR_BITS-1:0] perf_mshr_stalls;
|
|
reg [`PERF_CTR_BITS-1:0] perf_pipe_stalls;
|
|
reg [`PERF_CTR_BITS-1:0] perf_crsp_stalls;
|
|
|
|
always @(posedge clk) begin
|
|
if (reset) begin
|
|
perf_core_reads <= 0;
|
|
perf_core_writes <= 0;
|
|
perf_read_misses <= 0;
|
|
perf_write_misses <= 0;
|
|
perf_mshr_stalls <= 0;
|
|
perf_pipe_stalls <= 0;
|
|
perf_crsp_stalls <= 0;
|
|
end else begin
|
|
perf_core_reads <= perf_core_reads + `PERF_CTR_BITS'(perf_core_reads_per_cycle);
|
|
perf_core_writes <= perf_core_writes + `PERF_CTR_BITS'(perf_core_writes_per_cycle);
|
|
perf_read_misses <= perf_read_misses + `PERF_CTR_BITS'(perf_read_miss_per_cycle);
|
|
perf_write_misses <= perf_write_misses+ `PERF_CTR_BITS'(perf_write_miss_per_cycle);
|
|
perf_mshr_stalls <= perf_mshr_stalls + `PERF_CTR_BITS'(perf_mshr_stall_per_cycle);
|
|
perf_pipe_stalls <= perf_pipe_stalls + `PERF_CTR_BITS'(perf_pipe_stall_per_cycle);
|
|
perf_crsp_stalls <= perf_crsp_stalls + `PERF_CTR_BITS'(perf_crsp_stall_per_cycle);
|
|
end
|
|
end
|
|
|
|
assign perf_cache_if.reads = perf_core_reads;
|
|
assign perf_cache_if.writes = perf_core_writes;
|
|
assign perf_cache_if.read_misses = perf_read_misses;
|
|
assign perf_cache_if.write_misses = perf_write_misses;
|
|
assign perf_cache_if.mshr_stalls = perf_mshr_stalls;
|
|
assign perf_cache_if.pipe_stalls = perf_pipe_stalls;
|
|
assign perf_cache_if.crsp_stalls = perf_crsp_stalls;
|
|
`endif
|
|
|
|
endmodule
|