323 lines
12 KiB
Verilog
323 lines
12 KiB
Verilog
`include "VX_define.vh"
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module VX_lsu_unit #(
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parameter CORE_ID = 0
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) (
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`SCOPE_IO_VX_lsu_unit
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input wire clk,
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input wire reset,
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// Dcache interface
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VX_dcache_core_req_if dcache_req_if,
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VX_dcache_core_rsp_if dcache_rsp_if,
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// inputs
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VX_lsu_req_if lsu_req_if,
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// outputs
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VX_commit_if ld_commit_if,
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VX_commit_if st_commit_if
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);
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`UNUSED_PARAM (CORE_ID)
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wire req_valid;
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wire [`NUM_THREADS-1:0] req_tmask;
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wire [`NUM_THREADS-1:0][31:0] req_addr;
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wire [`LSU_BITS-1:0] req_type;
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wire [`NUM_THREADS-1:0][31:0] req_data;
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wire [`NR_BITS-1:0] req_rd;
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wire req_wb;
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wire [`NW_BITS-1:0] req_wid;
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wire [31:0] req_pc;
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wire req_is_dup;
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wire [`NUM_THREADS-1:0][31:0] full_address;
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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assign full_address[i] = lsu_req_if.base_addr[i] + lsu_req_if.offset;
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end
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wire [`NUM_THREADS-1:0] addr_matches;
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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assign addr_matches[i] = (full_address[0][31:2] == full_address[i][31:2]) || ~lsu_req_if.tmask[i];
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end
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wire is_dup_load = lsu_req_if.wb && lsu_req_if.tmask[0] && (& addr_matches);
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wire ready_in;
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wire stall_in = ~ready_in && req_valid;
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VX_pipe_register #(
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.DATAW (1 + 1 + `NW_BITS + `NUM_THREADS + 32 + (`NUM_THREADS * 32) + `LSU_BITS + `NR_BITS + 1 + (`NUM_THREADS * 32)),
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.RESETW (1)
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) req_pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (!stall_in),
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.data_in ({lsu_req_if.valid, is_dup_load, lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, full_address, lsu_req_if.op_type, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.store_data}),
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.data_out ({req_valid, req_is_dup, req_wid, req_tmask, req_pc, req_addr, req_type, req_rd, req_wb, req_data})
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);
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// Can accept new request?
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assign lsu_req_if.ready = ~stall_in;
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wire [`NW_BITS-1:0] rsp_wid;
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wire [31:0] rsp_pc;
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wire [`NR_BITS-1:0] rsp_rd;
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wire rsp_wb;
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wire [`LSU_BITS-1:0] rsp_type;
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wire rsp_is_dup;
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`UNUSED_VAR (rsp_type)
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reg [`LSUQ_SIZE-1:0][`NUM_THREADS-1:0] rsp_rem_mask;
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wire [`NUM_THREADS-1:0] rsp_rem_mask_n;
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wire [`NUM_THREADS-1:0] rsp_tmask;
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reg [`NUM_THREADS-1:0] req_sent_mask;
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wire req_ready_all;
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wire [`DCORE_TAG_ID_BITS-1:0] mbuf_waddr, mbuf_raddr;
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wire mbuf_full;
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wire [`NUM_THREADS-1:0][1:0] req_offset, rsp_offset;
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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assign req_offset[i] = req_addr[i][1:0];
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end
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wire [`NUM_THREADS-1:0] dcache_req_fire = dcache_req_if.valid & dcache_req_if.ready;
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wire dcache_rsp_fire = (| dcache_rsp_if.valid) && dcache_rsp_if.ready;
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wire mbuf_push = (| dcache_req_fire)
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&& (0 == req_sent_mask) // first submission only
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&& req_wb; // loads only
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wire mbuf_pop = dcache_rsp_fire && (0 == rsp_rem_mask_n);
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assign mbuf_raddr = dcache_rsp_if.tag[`DCORE_TAG_ID_BITS-1:0];
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VX_index_buffer #(
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.DATAW (`NW_BITS + 32 + `NUM_THREADS + `NR_BITS + 1 + `LSU_BITS + (`NUM_THREADS * 2) + 1),
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.SIZE (`LSUQ_SIZE)
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) req_metadata (
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.clk (clk),
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.reset (reset),
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.write_addr (mbuf_waddr),
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.acquire_slot (mbuf_push),
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.read_addr (mbuf_raddr),
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.write_data ({req_wid, req_pc, req_tmask, req_rd, req_wb, req_type, req_offset, req_is_dup}),
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.read_data ({rsp_wid, rsp_pc, rsp_tmask, rsp_rd, rsp_wb, rsp_type, rsp_offset, rsp_is_dup}),
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.release_addr (mbuf_raddr),
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.release_slot (mbuf_pop),
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.full (mbuf_full),
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`UNUSED_PIN (empty)
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);
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assign req_ready_all = &(dcache_req_if.ready | req_sent_mask | ~req_tmask);
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wire [`NUM_THREADS-1:0] req_sent_dup = {{(`NUM_THREADS-1){dcache_req_fire[0] && req_is_dup}}, 1'b0};
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always @(posedge clk) begin
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if (reset) begin
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req_sent_mask <= 0;
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end else begin
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if (req_ready_all)
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req_sent_mask <= 0;
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else
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req_sent_mask <= req_sent_mask | dcache_req_fire | req_sent_dup;
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end
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end
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wire is_req_start = (0 == req_sent_mask);
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// need to hold the acquired tag index until the full request is submitted
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reg [`DCORE_TAG_ID_BITS-1:0] req_tag_hold;
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wire [`DCORE_TAG_ID_BITS-1:0] req_tag = is_req_start ? mbuf_waddr : req_tag_hold;
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always @(posedge clk) begin
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if (mbuf_push) begin
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req_tag_hold <= mbuf_waddr;
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end
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end
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wire [`NUM_THREADS-1:0] req_tmask_dup = req_tmask & {{(`NUM_THREADS-1){~req_is_dup}}, 1'b1};
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assign rsp_rem_mask_n = rsp_rem_mask[mbuf_raddr] & ~dcache_rsp_if.valid;
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always @(posedge clk) begin
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if (mbuf_push) begin
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rsp_rem_mask[mbuf_waddr] <= req_tmask_dup;
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end
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if (dcache_rsp_fire) begin
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rsp_rem_mask[mbuf_raddr] <= rsp_rem_mask_n;
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end
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end
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// ensure all dependencies for the requests are resolved
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wire req_dep_ready = (req_wb && (~mbuf_full || ~is_req_start))
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|| (~req_wb && st_commit_if.ready);
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// DCache Request
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reg [`NUM_THREADS-1:0][29:0] mem_req_addr;
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reg [`NUM_THREADS-1:0][3:0] mem_req_byteen;
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reg [`NUM_THREADS-1:0][31:0] mem_req_data;
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always @(*) begin
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for (integer i = 0; i < `NUM_THREADS; i++) begin
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mem_req_byteen[i] = {4{req_wb}};
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case (`LSU_WSIZE(req_type))
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0: mem_req_byteen[i][req_offset[i]] = 1;
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1: begin
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mem_req_byteen[i][req_offset[i]] = 1;
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mem_req_byteen[i][{req_addr[i][1], 1'b1}] = 1;
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end
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default : mem_req_byteen[i] = {4{1'b1}};
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endcase
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mem_req_data[i] = 'x;
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case (req_offset[i])
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1: mem_req_data[i][31:8] = req_data[i][23:0];
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2: mem_req_data[i][31:16] = req_data[i][15:0];
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3: mem_req_data[i][31:24] = req_data[i][7:0];
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default: mem_req_data[i] = req_data[i];
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endcase
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mem_req_addr[i] = req_addr[i][31:2];
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end
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end
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assign dcache_req_if.valid = {`NUM_THREADS{req_valid && req_dep_ready}} & req_tmask_dup & ~req_sent_mask;
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assign dcache_req_if.rw = {`NUM_THREADS{~req_wb}};
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assign dcache_req_if.addr = mem_req_addr;
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assign dcache_req_if.byteen = mem_req_byteen;
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assign dcache_req_if.data = mem_req_data;
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`ifdef DBG_CACHE_REQ_INFO
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assign dcache_req_if.tag = {`NUM_THREADS{req_pc, req_wid, req_tag}};
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`else
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assign dcache_req_if.tag = {`NUM_THREADS{req_tag}};
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`endif
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assign ready_in = req_dep_ready && req_ready_all;
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// send store commit
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wire is_store_rsp = req_valid && ~req_wb && req_ready_all;
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assign st_commit_if.valid = is_store_rsp;
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assign st_commit_if.wid = req_wid;
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assign st_commit_if.tmask = req_tmask;
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assign st_commit_if.PC = req_pc;
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assign st_commit_if.rd = 0;
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assign st_commit_if.wb = 0;
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assign st_commit_if.eop = 1'b1;
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assign st_commit_if.data = 0;
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// load response formatting
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reg [`NUM_THREADS-1:0][31:0] rsp_data;
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wire [`NUM_THREADS-1:0] rsp_tmask_qual;
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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wire [31:0] src_data = (i == 0 || rsp_is_dup) ? dcache_rsp_if.data[0] : dcache_rsp_if.data[i];
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reg [31:0] rsp_data_shifted;
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always @(*) begin
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rsp_data_shifted[31:16] = src_data[31:16];
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rsp_data_shifted[15:0] = rsp_offset[i][1] ? src_data[31:16] : src_data[15:0];
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rsp_data_shifted[7:0] = rsp_offset[i][0] ? rsp_data_shifted[15:8] : rsp_data_shifted[7:0];
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end
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always @(*) begin
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case (`LSU_FMT(rsp_type))
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`FMT_B: rsp_data[i] = 32'(signed'(rsp_data_shifted[7:0]));
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`FMT_H: rsp_data[i] = 32'(signed'(rsp_data_shifted[15:0]));
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`FMT_BU: rsp_data[i] = 32'(unsigned'(rsp_data_shifted[7:0]));
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`FMT_HU: rsp_data[i] = 32'(unsigned'(rsp_data_shifted[15:0]));
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default: rsp_data[i] = rsp_data_shifted;
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endcase
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end
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end
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assign rsp_tmask_qual = rsp_is_dup ? rsp_tmask : dcache_rsp_if.valid;
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// send load commit
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wire load_rsp_stall = ~ld_commit_if.ready && ld_commit_if.valid;
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VX_pipe_register #(
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.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1),
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.RESETW (1)
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) rsp_pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (!load_rsp_stall),
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.data_in ({(| dcache_rsp_if.valid), rsp_wid, rsp_tmask_qual, rsp_pc, rsp_rd, rsp_wb, rsp_data, mbuf_pop}),
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.data_out ({ld_commit_if.valid, ld_commit_if.wid, ld_commit_if.tmask, ld_commit_if.PC, ld_commit_if.rd, ld_commit_if.wb, ld_commit_if.data, ld_commit_if.eop})
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);
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// Can accept new cache response?
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assign dcache_rsp_if.ready = ~load_rsp_stall;
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// scope registration
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`SCOPE_ASSIGN (dcache_req_fire, dcache_req_fire);
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`SCOPE_ASSIGN (dcache_req_wid, req_wid);
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`SCOPE_ASSIGN (dcache_req_pc, req_pc);
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`SCOPE_ASSIGN (dcache_req_addr, req_addr);
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`SCOPE_ASSIGN (dcache_req_rw, ~req_wb);
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`SCOPE_ASSIGN (dcache_req_byteen,dcache_req_if.byteen);
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`SCOPE_ASSIGN (dcache_req_data, dcache_req_if.data);
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`SCOPE_ASSIGN (dcache_req_tag, req_tag);
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`SCOPE_ASSIGN (dcache_rsp_fire, dcache_rsp_if.valid & {`NUM_THREADS{dcache_rsp_if.ready}});
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`SCOPE_ASSIGN (dcache_rsp_data, dcache_rsp_if.data);
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`SCOPE_ASSIGN (dcache_rsp_tag, mbuf_raddr);
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`ifdef DBG_PRINT_CORE_DCACHE
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`IGNORE_WARNINGS_BEGIN
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reg [`LSUQ_SIZE-1:0][`DCORE_TAG_WIDTH:0] pending_reqs;
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`IGNORE_WARNINGS_END
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always @(posedge clk) begin
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if (reset) begin
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pending_reqs <= '0;
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end else if (mbuf_push) begin
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pending_reqs[mbuf_waddr] <= {dcache_req_if.tag[0], 1'b1};
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end else if (mbuf_pop) begin
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pending_reqs[mbuf_raddr] <= '0;
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end
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end
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always @(posedge clk) begin
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if ((| dcache_req_fire)) begin
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if (dcache_req_if.rw[0]) begin
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$write("%t: D$%0d Wr Req: wid=%0d, PC=%0h, tmask=%b, addr=", $time, CORE_ID, req_wid, req_pc, dcache_req_fire);
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`PRINT_ARRAY1D(req_addr, `NUM_THREADS);
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$write(", tag=%0h, byteen=%0h, data=", dcache_req_if.tag[0], dcache_req_if.byteen);
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`PRINT_ARRAY1D(dcache_req_if.data, `NUM_THREADS);
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$write("\n");
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end else begin
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$write("%t: D$%0d Rd Req: wid=%0d, PC=%0h, tmask=%b, addr=", $time, CORE_ID, req_wid, req_pc, dcache_req_fire);
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`PRINT_ARRAY1D(req_addr, `NUM_THREADS);
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$write(", tag=%0h, byteen=%0h, rd=%0d, is_dup=%b\n", dcache_req_if.tag[0], dcache_req_if.byteen, req_rd, req_is_dup);
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end
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end
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if (dcache_rsp_fire) begin
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$write("%t: D$%0d Rsp: valid=%b, wid=%0d, PC=%0h, tag=%0h, rd=%0d, data=",
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$time, CORE_ID, dcache_rsp_if.valid, rsp_wid, rsp_pc, dcache_rsp_if.tag, rsp_rd);
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`PRINT_ARRAY1D(dcache_rsp_if.data, `NUM_THREADS);
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$write(", is_dup=%b\n", rsp_is_dup);
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end
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if (mbuf_full) begin
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$write("%t: *** D$%0d queue-full:", $time, CORE_ID);
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for (integer j = 0; j < `LSUQ_SIZE; j++) begin
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if (pending_reqs[j][0]) begin
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$write(" %0d->%0h", j, pending_reqs[j][1 +: `DCORE_TAG_WIDTH]);
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end
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end
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$write("\n");
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end
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end
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`endif
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endmodule |