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5c83c594c141e2e2cc651da5af2ba8a405b57d4b
vortex/hw/rtl
History
Blaise Tine 5c83c594c1 minor update
2021-01-07 17:25:59 -08:00
..
afu
minor update
2021-01-06 23:30:30 -08:00
cache
minor update
2021-01-06 19:59:04 -08:00
fp_cores
minor update
2021-01-06 19:59:04 -08:00
interfaces
scoreboard optimization - using writeback's end-of-packet status
2020-12-30 06:47:56 -08:00
libs
minor update
2021-01-07 17:25:59 -08:00
tex_unit
modelsim fixes && pipeline optimization
2020-07-28 14:20:23 -07:00
.DS_Store
project directories reorganization
2020-04-14 06:35:20 -04:00
.gitignore
fix opae build
2020-04-20 12:51:42 -07:00
Vortex.v
minor update
2021-01-07 17:25:59 -08:00
VX_alu_unit.v
scoreboard optimization - using writeback's end-of-packet status
2020-12-30 06:47:56 -08:00
VX_cluster.v
minor update
2021-01-07 17:25:59 -08:00
VX_commit.v
FPU float<->int conversion optimization
2020-12-29 15:37:45 -08:00
VX_config.vh
minor update
2021-01-06 21:39:15 -08:00
VX_core.v
added support for write-through cache, removed cache snooping support
2020-12-23 23:51:02 -08:00
VX_csr_arb.v
added support for write-through cache, removed cache snooping support
2020-12-23 23:51:02 -08:00
VX_csr_data.v
vx_spawn_warps redesign using opencl's style scheduler
2021-01-01 14:13:48 -05:00
VX_csr_io_arb.v
scoreboard optimization - using writeback's end-of-packet status
2020-12-30 06:47:56 -08:00
VX_csr_unit.v
fixed loader script stack setup
2020-12-31 22:37:20 -05:00
VX_databus_arb.v
minor update
2021-01-06 21:39:15 -08:00
VX_decode.v
critical path optimization - fpga fmax @4c = ~212 mhz
2020-12-26 03:28:32 -08:00
VX_define.vh
cache fill response address is the mshr's top address, no need to store it
2021-01-03 00:57:24 -05:00
VX_execute.v
merging perf counters
2020-12-08 21:02:39 -08:00
VX_fetch.v
scope fixes
2020-10-13 08:44:55 -07:00
VX_fpu_unit.v
minor update
2021-01-06 23:37:24 -08:00
VX_gpr_ram_f.v
minor update
2021-01-01 20:24:18 -08:00
VX_gpr_ram_i.v
fixed register file initialization to zero synthesis inference
2020-12-10 00:27:56 -08:00
VX_gpr_stage.v
minor update
2021-01-01 20:24:18 -08:00
VX_gpu_unit.v
scoreboard optimization - using writeback's end-of-packet status
2020-12-30 06:47:56 -08:00
VX_ibuffer.v
scoreboard optimization - using writeback's end-of-packet status
2020-12-30 06:47:56 -08:00
VX_icache_stage.v
cache optimization - moved read requests to stage1 and eliminating stage3
2020-12-31 07:40:58 -08:00
VX_instr_demux.v
FPU float<->int conversion optimization
2020-12-29 15:37:45 -08:00
VX_ipdom_stack.v
critical path optimization - fpga fmax @4c = ~212 mhz
2020-12-26 03:28:32 -08:00
VX_issue.v
cache optimization - moved read requests to stage1 and eliminating stage3
2020-12-31 07:40:58 -08:00
VX_lsu_unit.v
minor update
2021-01-06 21:39:15 -08:00
VX_mem_arb.v
performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
2020-12-19 02:45:06 -08:00
VX_mem_unit.v
speeding up simulation using dedicated full dpi-based FPU core
2021-01-06 18:44:06 -08:00
VX_mul_unit.v
scoreboard optimization - using writeback's end-of-packet status
2020-12-30 06:47:56 -08:00
VX_pipeline.v
added support for write-through cache, removed cache snooping support
2020-12-23 23:51:02 -08:00
VX_platform.vh
scratchpad optimization for stack access using custom bank offset aligned to stack size
2021-01-02 16:00:00 -05:00
VX_print_instr.vh
scratchpad optimization for stack access using custom bank offset aligned to stack size
2021-01-02 16:00:00 -05:00
VX_scope.vh
cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
2020-11-02 01:50:12 -08:00
VX_scoreboard.v
scoreboard optimization - using writeback's end-of-packet status
2020-12-30 06:47:56 -08:00
VX_types.vh
FPU float<->int conversion optimization
2020-12-29 15:37:45 -08:00
VX_warp_sched.v
FPU float<->int conversion optimization
2020-12-29 15:37:45 -08:00
VX_writeback.v
scoreboard optimization - using writeback's end-of-packet status
2020-12-30 06:47:56 -08:00