303 lines
9.7 KiB
Verilog
303 lines
9.7 KiB
Verilog
`include "VX_platform.vh"
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`TRACING_OFF
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module VX_dp_ram #(
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parameter DATAW = 1,
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parameter SIZE = 1,
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parameter BYTEENW = 1,
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parameter BUFFERED = 0,
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parameter RWCHECK = 1,
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parameter ADDRW = $clog2(SIZE),
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parameter SIZEW = $clog2(SIZE+1),
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parameter FASTRAM = 0
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) (
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input wire clk,
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input wire [ADDRW-1:0] waddr,
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input wire [ADDRW-1:0] raddr,
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input wire wren,
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input wire [BYTEENW-1:0] byteen,
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input wire rden,
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input wire [DATAW-1:0] din,
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output wire [DATAW-1:0] dout
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);
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`STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter"))
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localparam DATA32W = DATAW / 32;
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localparam BYTEEN32W = BYTEENW / 4;
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//`ifndef QUARTUS
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if (FASTRAM) begin
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if (BUFFERED) begin
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reg [DATAW-1:0] dout_r;
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if (BYTEENW > 1) begin
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`USE_FAST_BRAM reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
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always @(posedge clk) begin
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if (wren) begin
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for (integer j = 0; j < BYTEEN32W; j++) begin
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for (integer i = 0; i < 4; i++) begin
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if (byteen[j * 4 + i])
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mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
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end
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end
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end
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if (rden)
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dout_r <= mem[raddr];
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end
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end else begin
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`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
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always @(posedge clk) begin
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if (wren && byteen)
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mem[waddr] <= din;
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if (rden)
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dout_r <= mem[raddr];
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end
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end
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assign dout = dout_r;
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end else begin
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`UNUSED_VAR (rden)
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if (RWCHECK) begin
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if (BYTEENW > 1) begin
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`USE_FAST_BRAM reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
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always @(posedge clk) begin
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if (wren) begin
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for (integer j = 0; j < BYTEEN32W; j++) begin
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for (integer i = 0; i < 4; i++) begin
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if (byteen[j * 4 + i])
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mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
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end
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end
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end
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end
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assign dout = mem[raddr];
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end else begin
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`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
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always @(posedge clk) begin
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if (wren && byteen)
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mem[waddr] <= din;
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end
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assign dout = mem[raddr];
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end
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end else begin
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if (BYTEENW > 1) begin
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`USE_FAST_BRAM `NO_RW_RAM_CHECK reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
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always @(posedge clk) begin
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if (wren) begin
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for (integer j = 0; j < BYTEEN32W; j++) begin
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for (integer i = 0; i < 4; i++) begin
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if (byteen[j * 4 + i])
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mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
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end
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end
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end
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end
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assign dout = mem[raddr];
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end else begin
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`USE_FAST_BRAM `NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0];
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always @(posedge clk) begin
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if (wren && byteen)
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mem[waddr] <= din;
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end
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assign dout = mem[raddr];
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end
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end
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end
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end else begin
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if (BUFFERED) begin
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reg [DATAW-1:0] dout_r;
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if (BYTEENW > 1) begin
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reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
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always @(posedge clk) begin
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if (wren) begin
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for (integer j = 0; j < BYTEEN32W; j++) begin
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for (integer i = 0; i < 4; i++) begin
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if (byteen[j * 4 + i])
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mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
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end
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end
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end
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if (rden)
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dout_r <= mem[raddr];
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end
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end else begin
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reg [DATAW-1:0] mem [SIZE-1:0];
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always @(posedge clk) begin
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if (wren && byteen)
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mem[waddr] <= din;
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if (rden)
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dout_r <= mem[raddr];
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end
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end
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assign dout = dout_r;
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end else begin
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`UNUSED_VAR (rden)
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if (RWCHECK) begin
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if (BYTEENW > 1) begin
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reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
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always @(posedge clk) begin
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if (wren) begin
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for (integer j = 0; j < BYTEEN32W; j++) begin
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for (integer i = 0; i < 4; i++) begin
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if (byteen[j * 4 + i])
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mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
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end
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end
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end
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end
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assign dout = mem[raddr];
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end else begin
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reg [DATAW-1:0] mem [SIZE-1:0];
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always @(posedge clk) begin
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if (wren && byteen)
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mem[waddr] <= din;
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end
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assign dout = mem[raddr];
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end
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end else begin
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if (BYTEENW > 1) begin
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`NO_RW_RAM_CHECK reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
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always @(posedge clk) begin
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if (wren) begin
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for (integer j = 0; j < BYTEEN32W; j++) begin
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for (integer i = 0; i < 4; i++) begin
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if (byteen[j * 4 + i])
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mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
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end
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end
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end
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end
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assign dout = mem[raddr];
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end else begin
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`NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0];
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always @(posedge clk) begin
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if (wren && byteen)
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mem[waddr] <= din;
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end
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assign dout = mem[raddr];
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end
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end
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end
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end
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/*`else
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localparam OUTDATA_REG_B = BUFFERED ? "CLOCK0" : "UNREGISTERED";
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localparam RAM_BLOCK_TYPE = FASTRAM ? "MLAB" : "AUTO";
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if (RWCHECK) begin
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altsyncram #(
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.init_file (),
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.operation_mode ("DUAL_PORT"),
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.numwords_a (SIZE),
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.numwords_b (SIZE),
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.widthad_a (ADDRW),
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.widthad_b (ADDRW),
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.width_a (DATAW),
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.width_b (DATAW),
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.width_byteena_a(BYTEENW),
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.address_reg_b ("CLOCK0"),
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.outdata_reg_b (OUTDATA_REG_B),
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.ram_block_type (RAM_BLOCK_TYPE)
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) mem (
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.clocken0 (1'b1),
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.clocken1 (),
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.clocken2 (),
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.clocken3 (),
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.clock0 (clk),
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.clock1 (),
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.address_a (waddr),
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.address_b (raddr),
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.byteena_a (byteen),
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.byteena_b (1'b1),
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.wren_a (wren),
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.wren_b (1'b0),
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.data_a (din),
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.data_b (),
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.rden_a (),
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.rden_b (1'b1),
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.q_a (),
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.q_b (dout),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.eccstatus ()
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);
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end else begin
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`NO_RW_RAM_CHECK altsyncram #(
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.init_file (),
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.operation_mode ("DUAL_PORT"),
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.numwords_a (SIZE),
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.numwords_b (SIZE),
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.widthad_a (ADDRW),
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.widthad_b (ADDRW),
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.width_a (DATAW),
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.width_b (DATAW),
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.width_byteena_a(BYTEENW),
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.outdata_reg_b (OUTDATA_REG_B),
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.ram_block_type (RAM_BLOCK_TYPE)
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) mem (
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.clock0 (clk),
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.clock1 (clk),
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.address_a (waddr),
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.address_b (raddr),
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.byteena_a (byteen),
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.byteena_b (1'b1),
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.wren_a (wren),
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.wren_b (1'b0),
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.data_a (din),
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.data_b (),
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.rden_a (),
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.rden_b (1'b1),
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.q_a (),
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.q_b (dout),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.eccstatus ()
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);
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end
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`endif*/
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endmodule
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`TRACING_ON |