209 lines
7.2 KiB
Verilog
209 lines
7.2 KiB
Verilog
`include "VX_define.v"
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module VX_alu(
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input wire clk,
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input wire reset,
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input wire[31:0] in_1,
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input wire[31:0] in_2,
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input wire in_rs2_src,
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input wire[31:0] in_itype_immed,
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input wire[19:0] in_upper_immed,
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input wire[4:0] in_alu_op,
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input wire[31:0] in_curr_PC,
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output reg[31:0] out_alu_result,
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output reg out_alu_stall
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);
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localparam div_pipeline_len = 20;
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localparam mul_pipeline_len = 8;
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wire[31:0] unsigned_div_result;
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wire[31:0] unsigned_rem_result;
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wire[31:0] signed_div_result;
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wire[31:0] signed_rem_result;
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wire[63:0] mul_data_a, mul_data_b;
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wire[63:0] mul_result;
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wire[31:0] ALU_in1;
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wire[31:0] ALU_in2;
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VX_divide #(
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.WIDTHN(32),
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.WIDTHD(32),
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.SPEED("HIGHEST"),
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.PIPELINE(div_pipeline_len)
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) unsigned_div (
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.clock(clk),
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.aclr(1'b0),
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.clken(1'b1), // TODO this could be disabled on inactive instructions
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.numer(ALU_in1),
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.denom(ALU_in2),
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.quotient(unsigned_div_result),
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.remainder(unsigned_rem_result)
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);
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VX_divide #(
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.WIDTHN(32),
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.WIDTHD(32),
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.NREP("SIGNED"),
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.DREP("SIGNED"),
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.SPEED("HIGHEST"),
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.PIPELINE(div_pipeline_len)
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) signed_div (
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.clock(clk),
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.aclr(1'b0),
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.clken(1'b1), // TODO this could be disabled on inactive instructions
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.numer(ALU_in1),
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.denom(ALU_in2),
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.quotient(signed_div_result),
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.remainder(signed_rem_result)
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);
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VX_mult #(
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.WIDTHA(64),
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.WIDTHB(64),
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.WIDTHP(64),
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.SPEED("HIGHEST"),
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.FORCE_LE("YES"),
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.PIPELINE(mul_pipeline_len)
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) multiplier (
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.clock(clk),
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.aclr(1'b0),
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.clken(1'b1), // TODO this could be disabled on inactive instructions
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.dataa(mul_data_a),
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.datab(mul_data_b),
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.result(mul_result)
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);
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// MUL, MULH (signed*signed), MULHSU (signed*unsigned), MULHU (unsigned*unsigned)
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wire[63:0] alu_in1_signed = {{32{ALU_in1[31]}}, ALU_in1};
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wire[63:0] alu_in2_signed = {{32{ALU_in2[31]}}, ALU_in2};
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assign mul_data_a = (in_alu_op == `MULHU) ? {32'b0, ALU_in1} : alu_in1_signed;
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assign mul_data_b = (in_alu_op == `MULHU || in_alu_op == `MULHSU) ? {32'b0, ALU_in2} : alu_in2_signed;
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reg [15:0] curr_inst_delay;
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reg [15:0] inst_delay;
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reg inst_was_stalling;
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wire inst_delay_stall = inst_was_stalling ? inst_delay != 0 : curr_inst_delay != 0;
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assign out_alu_stall = inst_delay_stall;
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always @(*) begin
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case(in_alu_op)
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`DIV,
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`DIVU,
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`REM,
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`REMU: curr_inst_delay = div_pipeline_len;
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`MUL,
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`MULH,
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`MULHSU,
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`MULHU: curr_inst_delay = mul_pipeline_len;
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default: curr_inst_delay = 0;
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endcase // in_alu_op
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end
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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inst_delay <= 0;
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inst_was_stalling <= 0;
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end
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else if (inst_delay_stall) begin
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if (inst_was_stalling) begin
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if (inst_delay > 0)
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inst_delay <= inst_delay - 1;
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end
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else begin
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inst_was_stalling <= 1;
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inst_delay <= curr_inst_delay - 1;
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end
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end
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else begin
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inst_was_stalling <= 0;
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end
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end
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`ifdef SYN_FUNC
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wire which_in2;
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wire[31:0] upper_immed;
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assign which_in2 = in_rs2_src == `RS2_IMMED;
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assign ALU_in1 = in_1;
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assign ALU_in2 = which_in2 ? in_itype_immed : in_2;
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assign upper_immed = {in_upper_immed, {12{1'b0}}};
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always @(in_alu_op or ALU_in1 or ALU_in2) begin
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case(in_alu_op)
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`ADD: out_alu_result = $signed(ALU_in1) + $signed(ALU_in2);
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`SUB: out_alu_result = $signed(ALU_in1) - $signed(ALU_in2);
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`SLLA: out_alu_result = ALU_in1 << ALU_in2[4:0];
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`SLT: out_alu_result = ($signed(ALU_in1) < $signed(ALU_in2)) ? 32'h1 : 32'h0;
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`SLTU: out_alu_result = ALU_in1 < ALU_in2 ? 32'h1 : 32'h0;
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`XOR: out_alu_result = ALU_in1 ^ ALU_in2;
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`SRL: out_alu_result = ALU_in1 >> ALU_in2[4:0];
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`SRA: out_alu_result = $signed(ALU_in1) >>> ALU_in2[4:0];
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`OR: out_alu_result = ALU_in1 | ALU_in2;
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`AND: out_alu_result = ALU_in2 & ALU_in1;
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`SUBU: out_alu_result = (ALU_in1 >= ALU_in2) ? 32'h0 : 32'hffffffff;
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`LUI_ALU: out_alu_result = upper_immed;
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`AUIPC_ALU: out_alu_result = $signed(in_curr_PC) + $signed(upper_immed);
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// TODO profitable to roll these exceptional cases into inst_delay to avoid pipeline when possible?
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`MUL: out_alu_result = mul_result[31:0];
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`MULH: out_alu_result = mul_result[63:32];
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`MULHSU: out_alu_result = mul_result[63:32];
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`MULHU: out_alu_result = mul_result[63:32];
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`DIV: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : signed_div_result;
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`DIVU: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : unsigned_div_result;
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`REM: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : signed_rem_result;
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`REMU: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : unsigned_rem_result;
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default: out_alu_result = 32'h0;
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endcase // in_alu_op
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end
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`else
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wire which_in2;
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wire[31:0] upper_immed;
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assign which_in2 = in_rs2_src == `RS2_IMMED;
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assign ALU_in1 = in_1;
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assign ALU_in2 = which_in2 ? in_itype_immed : in_2;
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assign upper_immed = {in_upper_immed, {12{1'b0}}};
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always @(in_alu_op or ALU_in1 or ALU_in2) begin
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case(in_alu_op)
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`ADD: out_alu_result = $signed(ALU_in1) + $signed(ALU_in2);
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`SUB: out_alu_result = $signed(ALU_in1) - $signed(ALU_in2);
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`SLLA: out_alu_result = ALU_in1 << ALU_in2[4:0];
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`SLT: out_alu_result = ($signed(ALU_in1) < $signed(ALU_in2)) ? 32'h1 : 32'h0;
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`SLTU: out_alu_result = ALU_in1 < ALU_in2 ? 32'h1 : 32'h0;
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`XOR: out_alu_result = ALU_in1 ^ ALU_in2;
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`SRL: out_alu_result = ALU_in1 >> ALU_in2[4:0];
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`SRA: out_alu_result = $signed(ALU_in1) >>> ALU_in2[4:0];
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`OR: out_alu_result = ALU_in1 | ALU_in2;
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`AND: out_alu_result = ALU_in2 & ALU_in1;
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`SUBU: out_alu_result = (ALU_in1 >= ALU_in2) ? 32'h0 : 32'hffffffff;
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`LUI_ALU: out_alu_result = upper_immed;
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`AUIPC_ALU: out_alu_result = $signed(in_curr_PC) + $signed(upper_immed);
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// TODO profitable to roll these exceptional cases into inst_delay to avoid pipeline when possible?
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`MUL: out_alu_result = mul_result[31:0];
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`MULH: out_alu_result = mul_result[63:32];
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`MULHSU: out_alu_result = mul_result[63:32];
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`MULHU: out_alu_result = mul_result[63:32];
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`DIV: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : signed_div_result;
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`DIVU: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : unsigned_div_result;
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`REM: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : signed_rem_result;
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`REMU: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : unsigned_rem_result;
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default: out_alu_result = 32'h0;
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endcase // in_alu_op
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end
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`endif
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endmodule : VX_alu |