Blaise Tine
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acafcceb94
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fixed Modelsim build errors
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2020-03-26 03:56:44 -04:00 |
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wgulian3
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ca61801199
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Make ALU div/mul pipelines longer and support logic element multiplication mode for better long pipeline performance
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2020-02-22 20:16:13 -05:00 |
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wgulian3
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a099cb25cf
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Update multiply for not SYN_FUNC
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2020-02-21 23:20:04 -05:00 |
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wgulian3
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2c40874cc5
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Add multi-cycle compat module and use it in ALU
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2020-02-21 22:08:09 -05:00 |
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wgulian3
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3423e3189f
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Fix e2e building issues and increase division pipeline length
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2020-02-19 01:04:48 -05:00 |
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wgulian3
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e76d05f7ce
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Fix issues quartus synthesis issues
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2020-02-18 13:24:18 -05:00 |
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wgulian3
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d71f8fcc73
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Fix divide edge case in verilator and move divide modules out of SYN_FUNC block within alu.
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2020-02-18 13:02:46 -05:00 |
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wgulian3
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8318aff69f
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Support exec multi-cycle for div/mul
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2020-02-13 13:17:46 -05:00 |
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wgulian3
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9c7a9d88cf
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Replace div/rem expressions with divider modules in preparation for pipelining
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2020-02-04 11:54:06 -05:00 |
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Lyons, Ethan Tyler
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c8abd48458
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Synthesis Compatible
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2019-11-21 21:42:34 -05:00 |
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felsabbagh3
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88eab9e746
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Removed dependancy on
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2019-10-27 22:30:32 -04:00 |
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felsabbagh3
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1181af1df2
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Modelsim basic sim
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2019-10-26 00:34:57 -04:00 |
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felsabbagh3
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84f5ccb484
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Added CSR TID/WID reads
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2019-10-21 02:10:05 -04:00 |
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felsabbagh3
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ee83e6d8c8
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Moved GPR to back-end
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2019-10-14 19:08:32 -04:00 |
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felsabbagh3
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719ed25213
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Cleanup
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2019-03-31 16:30:37 -04:00 |
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felsabbagh3
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a3a3b21de7
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Using verilog For-loops + Passing all tests
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2019-03-30 22:09:03 -04:00 |
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felsabbagh3
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99a0792a0c
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Passing all tests with 2 threads
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2019-03-30 03:54:20 -04:00 |
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felsabbagh3
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7a528c5ef2
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Packing data wires + ALU module
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2019-03-26 19:17:11 -04:00 |
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