134 lines
3.9 KiB
Verilog
134 lines
3.9 KiB
Verilog
// To Do: Change way_id_out to an internal register which holds when in between access and finished.
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// Also add a bit about wheter the "Way ID" is valid / being held or if it is just default
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// Also make sure all possible output states are transmitted back to the bank correctly
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`define NUM_WORDS_PER_BLOCK 4
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`include "../VX_define.v"
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`include "VX_cache_data.v"
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module VX_Cache_Bank
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#(
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// parameter NUMBER_INDEXES = 256
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parameter NUMBER_INDEXES = 256
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)
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(
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clk,
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state,
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read_or_write, // Read = 0 | Write = 1
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valid_in,
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//write_from_mem,
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actual_index,
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o_tag,
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block_offset,
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writedata,
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fetched_writedata,
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readdata,
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hit,
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//miss,
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eviction_wb, // Need to evict
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eviction_addr, // What's the eviction tag
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data_evicted
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);
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parameter cache_entry = 14;
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parameter ways_per_set = 4;
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parameter Number_Blocks = 32;
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localparam CACHE_IDLE = 0; // Idle
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localparam SEND_MEM_REQ = 1; // Write back this block into memory
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localparam RECIV_MEM_RSP = 2;
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// Inputs
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input wire clk;
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input wire [3:0] state;
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//input wire write_from_mem;
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// Reading Data
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input wire[$clog2(NUMBER_INDEXES)-1:0] actual_index;
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input wire[16:0] o_tag; // When write_from_mem = 1, o_tag is the new tag
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input wire[1:0] block_offset;
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input wire[31:0] writedata;
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input wire valid_in;
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input wire read_or_write; // Specifies if it is a read or write operation
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input wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] fetched_writedata;
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// Outputs
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// Normal shit
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output wire[31:0] readdata;
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output wire hit;
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//output wire miss;
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// Eviction Data (Notice)
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output wire eviction_wb; // Need to evict
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output wire[31:0] eviction_addr; // What's the eviction tag
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// Eviction Data (Extraction)
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output wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_evicted;
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wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_use;
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wire[16:0] tag_use;
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wire[16:0] eviction_tag;
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wire valid_use;
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wire dirty_use;
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wire access;
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wire write_from_mem;
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wire miss; // -10/21
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assign miss = (tag_use != o_tag) && valid_use && valid_in;
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assign data_evicted = data_use;
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assign eviction_wb = miss && (dirty_use != 1'b0);
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assign eviction_tag = tag_use;
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assign access = (state == CACHE_IDLE) && valid_in;
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assign write_from_mem = (state == RECIV_MEM_RSP) && valid_in;
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assign readdata = (access) ? data_use[block_offset] : 32'b0; // Fix with actual data
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assign hit = (access && (tag_use == o_tag) && valid_use);
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//assign eviction_addr = {eviction_tag, actual_index, block_offset, 5'b0}; // Fix with actual data
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assign eviction_addr = {eviction_tag, actual_index, 7'b0}; // Fix with actual data
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wire[`NUM_WORDS_PER_BLOCK-1:0] we;
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wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_write;
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genvar g;
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for (g = 0; g < `NUM_WORDS_PER_BLOCK; g = g + 1) begin
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wire correct_block = (block_offset == g);
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assign we[g] = (read_or_write && ((access && correct_block) || (write_from_mem && !correct_block)) ) ? 1'b1 : 1'b0;
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//assign we[g] = (!(write_from_mem && correct_block) && ((write_from_mem || correct_block) && read_or_write == 1'b1)) ? 1 : 0; // added the "not"
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assign data_write[g] = write_from_mem ? fetched_writedata[g] : writedata;
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end
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VX_cache_data data_structures(
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.clk (clk),
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// Inputs
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.addr (actual_index),
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.we (we),
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.evict (write_from_mem),
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.data_write(data_write),
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.tag_write (o_tag),
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// Outputs
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.tag_use (tag_use),
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.data_use (data_use),
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.valid_use (valid_use),
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.dirty_use (dirty_use)
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);
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endmodule
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