126 lines
3.7 KiB
Makefile
126 lines
3.7 KiB
Makefile
###############################################################################
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#
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# ICARUS VERILOG & GTKWAVE MAKEFILE
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# MADE BY WILLIAM GIBB FOR HACDC
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# williamgibb@gmail.com
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#
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# USE THE FOLLOWING COMMANDS WITH THIS MAKEFILE
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# "make check" - compiles your verilog design - good for checking code
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# "make simulate" - compiles your design+TB & simulates your design
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# "make display" - compiles, simulates and displays waveforms
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#
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###############################################################################
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#
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# CHANGE THESE THREE LINES FOR YOUR DESIGN
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#
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#TOOL INPUT
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SRC = \
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vortex_tb.v \
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../VX_define.v \
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../interfaces/VX_branch_response_inter.v \
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../interfaces/VX_csr_req_inter.v \
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../interfaces/VX_csr_wb_inter.v \
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../interfaces/VX_dcache_request_inter.v \
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../interfaces/VX_dcache_response_inter.v \
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../interfaces/VX_dram_req_rsp_inter.v \
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../interfaces/VX_exec_unit_req_inter.v \
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../interfaces/VX_frE_to_bckE_req_inter.v \
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../interfaces/VX_gpr_clone_inter.v \
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../interfaces/VX_gpr_data_inter.v \
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../interfaces/VX_gpr_jal_inter.v \
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../interfaces/VX_gpr_read_inter.v \
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../interfaces/VX_gpr_wspawn_inter.v \
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../interfaces/VX_gpu_inst_req_inter.v \
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../interfaces/VX_icache_request_inter.v \
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../interfaces/VX_icache_response_inter.v \
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../interfaces/VX_inst_exec_wb_inter.v \
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../interfaces/VX_inst_mem_wb_inter.v \
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../interfaces/VX_inst_meta_inter.v \
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../interfaces/VX_jal_response_inter.v \
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../interfaces/VX_join_inter.v \
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../interfaces/VX_lsu_req_inter.v \
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../interfaces/VX_mem_req_inter.v \
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../interfaces/VX_mw_wb_inter.v \
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../interfaces/VX_warp_ctl_inter.v \
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../interfaces/VX_wb_inter.v \
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../interfaces/VX_wstall_inter.v \
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../VX_alu.v \
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../VX_back_end.v \
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../VX_csr_handler.v \
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../VX_csr_wrapper.v \
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../VX_decode.v \
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../VX_dmem_controller.v \
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../VX_execute_unit.v \
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../VX_fetch.v \
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../VX_front_end.v \
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../VX_generic_priority_encoder.v \
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../VX_generic_register.v \
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../VX_generic_stack.v \
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../VX_gpgpu_inst.v \
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../VX_gpr.v \
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../VX_gpr_stage.v \
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../VX_gpr_wrapper.v \
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../VX_inst_multiplex.v \
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../VX_lsu.v \
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../VX_lsu_addr_gen.v \
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../VX_one_counter.v \
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../VX_priority_encoder.v \
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../VX_priority_encoder_w_mask.v \
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../VX_rename.v \
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../VX_scheduler.v \
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../VX_warp.v \
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../VX_warp_scheduler.v \
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../VX_writeback.v \
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../Vortex.v \
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../byte_enabled_simple_dual_port_ram.v \
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../cache/VX_Cache_Bank.v \
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../cache/VX_Cache_Block_DM.v \
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../cache/VX_cache_bank_valid.v \
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../cache/VX_cache_data.v \
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../cache/VX_d_cache.v \
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../cache/VX_d_cache_encapsulate.v \
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../cache/VX_d_cache_tb.v \
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../cache/VX_generic_pe.v \
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../cache/bank.v \
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../cache/cache_set.v \
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../pipe_regs/VX_d_e_reg.v \
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../pipe_regs/VX_f_d_reg.v \
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../shared_memory/VX_bank_valids.v \
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../shared_memory/VX_priority_encoder_sm.v \
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../shared_memory/VX_set_bit.v \
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../shared_memory/VX_shared_memory.v \
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../shared_memory/VX_shared_memory_block.v
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TESTBENCH = vortex_tb.v
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TBOUTPUT = waves.lxt #THIS NEEDS TO MATCH THE OUTPUT FILE
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#FROM YOUR TESTBENCH
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###############################################################################
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# BE CAREFUL WHEN CHANGING ITEMS BELOW THIS LINE
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###############################################################################
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#TOOLS
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COMPILER = iverilog
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SIMULATOR = vvp
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VIEWER = gtkwave
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#TOOL OPTIONS
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COFLAGS = -v -o
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SFLAGS = -v
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SOUTPUT = -lxt #SIMULATOR OUTPUT TYPE
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#TOOL OUTPUT
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COUTPUT = compiler.out #COMPILER OUTPUT
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###############################################################################
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#MAKE DIRECTIVES
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check : $(TESTBENCH) $(SRC)
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$(COMPILER) -g2012 -o vortex $(SRC) -I../ -I.
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simulate: $(COUTPUT)
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$(SIMULATOR) $(SFLAGS) $(COUTPUT) $(SOUTPUT)
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display: $(TBOUTPUT)
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$(VIEWER) $(TBOUTPUT) &
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#MAKE DEPENDANCIES
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$(TBOUTPUT): $(COUTPUT)
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$(SIMULATOR) $(SOPTIONS) $(COUTPUT) $(SOUTPUT)
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$(COUTPUT): $(TESTBENCH) $(SRC)
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$(COMPILER) $(COFLAGS) $(COUTPUT) $(TESTBENCH) $(SRC)
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