88 lines
2.5 KiB
Verilog
88 lines
2.5 KiB
Verilog
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`include "VX_define.v"
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module VX_memory (
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input wire[31:0] in_alu_result,
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input wire[2:0] in_mem_read,
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input wire[2:0] in_mem_write,
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input wire[4:0] in_rd,
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input wire[1:0] in_wb,
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input wire[4:0] in_rs1,
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input wire[4:0] in_rs2,
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input wire[31:0] in_rd2,
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input wire[31:0] in_PC_next,
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input wire[31:0] in_curr_PC,
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input wire[31:0] in_branch_offset,
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input wire[2:0] in_branch_type,
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input wire in_valid,
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input wire[31:0] in_cache_driver_out_data,
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output wire[31:0] out_alu_result,
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output wire[31:0] out_mem_result,
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output wire[4:0] out_rd,
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output wire[1:0] out_wb,
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output wire[4:0] out_rs1,
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output wire[4:0] out_rs2,
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output reg out_branch_dir,
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output wire[31:0] out_branch_dest,
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output wire out_delay,
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output wire[31:0] out_PC_next,
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output wire out_valid,
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output wire[31:0] out_cache_driver_in_address,
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output wire[2:0] out_cache_driver_in_mem_read,
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output wire[2:0] out_cache_driver_in_mem_write,
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output wire[31:0] out_cache_driver_in_data
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);
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always @(in_mem_read, in_cache_driver_out_data) begin
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if (in_mem_read == `LW_MEM_READ) begin
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// $display("PC: %h ----> Received: %h", in_curr_PC, in_cache_driver_out_data);
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end
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end
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assign out_delay = 1'b0;
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assign out_cache_driver_in_address = in_alu_result;
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assign out_cache_driver_in_mem_read = in_mem_read;
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assign out_cache_driver_in_mem_write = in_mem_write;
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assign out_cache_driver_in_data = in_rd2;
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assign out_mem_result = in_cache_driver_out_data;
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assign out_alu_result = in_alu_result;
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assign out_rd = in_rd;
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assign out_wb = in_wb;
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assign out_rs1 = in_rs1;
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assign out_rs2 = in_rs2;
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assign out_PC_next = in_PC_next;
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assign out_valid = in_valid;
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assign out_branch_dest = $signed(in_curr_PC) + ($signed(in_branch_offset) << 1);
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always @(*) begin
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case(in_branch_type)
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`BEQ: out_branch_dir = (in_alu_result == 0) ? `TAKEN : `NOT_TAKEN;
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`BNE:
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begin
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out_branch_dir = (in_alu_result == 0) ? `NOT_TAKEN : `TAKEN;
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// $display("Branch @%h is: %h", in_curr_PC, out_branch_dir);
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end
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`BLT: out_branch_dir = (in_alu_result[31] == 0) ? `NOT_TAKEN : `TAKEN;
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`BGT: out_branch_dir = (in_alu_result[31] == 0) ? `TAKEN : `NOT_TAKEN;
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`BLTU: out_branch_dir = (in_alu_result[31] == 0) ? `NOT_TAKEN : `TAKEN;
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`BGTU: out_branch_dir = (in_alu_result[31] == 0) ? `TAKEN : `NOT_TAKEN;
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`NO_BRANCH: out_branch_dir = `NOT_TAKEN;
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default: out_branch_dir = `NOT_TAKEN;
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endcase // in_branch_type
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end
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endmodule // Memory
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