Blaise Tine
|
6213b1a910
|
vortex runtime console out implementation
|
2021-06-15 04:01:44 -04:00 |
|
Blaise Tine
|
76c4909ae9
|
minor update
|
2021-06-12 02:22:01 -04:00 |
|
Blaise Tine
|
3cc1190cd7
|
CSRs I/O refactoring
|
2021-06-11 03:08:07 -07:00 |
|
Blaise Tine
|
3071fb7a29
|
adding support for non-cacheable memory addressing
|
2021-06-06 13:35:55 -07:00 |
|
Blaise Tine
|
64848788a1
|
minor update
|
2021-04-26 20:34:28 -07:00 |
|
Blaise Tine
|
8543e3a8bf
|
code refactoring
|
2021-04-26 02:34:21 -07:00 |
|
Blaise Tine
|
8410c49f53
|
code refactoring: DRAM => MEM renaming
|
2021-04-26 00:58:48 -07:00 |
|
Blaise Tine
|
cad21a4b92
|
minor update
|
2021-04-24 01:17:38 -04:00 |
|
Blaise Tine
|
4cb98a25a7
|
enabling 128-bit dram bus
|
2021-04-24 00:31:27 -04:00 |
|
Blaise Tine
|
3f5fd6d394
|
using shiftreg-based skid buffers
|
2021-02-28 02:20:09 -08:00 |
|
Blaise Tine
|
700f9eea19
|
moving MUL unit into ALU unit
|
2021-02-23 13:49:02 -08:00 |
|
Blaise Tine
|
7560202f8b
|
cache bank refactoring - removing unecessary core response fifo & restoring single port data access
|
2021-02-21 21:47:46 -08:00 |
|
Blaise Tine
|
3c37db877a
|
cache specialization for in-order DRAM reponses
|
2021-02-13 20:23:29 -08:00 |
|
Blaise Tine
|
073964fdf7
|
minor update
|
2021-02-12 08:52:06 -08:00 |
|
Blaise Tine
|
665b97b810
|
multi-ported cache support for streaming
|
2021-02-08 16:13:32 -08:00 |
|
Blaise Tine
|
8775f63ec4
|
lkg build rollout with 16cores optimization on arria10
|
2021-01-24 16:49:22 -08:00 |
|
Blaise Tine
|
ce9ef840d6
|
minor updates
|
2021-01-18 04:22:40 -08:00 |
|
Blaise Tine
|
a046bd7a73
|
cache pipeline optimization
|
2021-01-17 17:19:52 -08:00 |
|
Blaise Tine
|
a69ba5ad7b
|
cache flush support
|
2021-01-17 05:50:29 -08:00 |
|
Blaise Tine
|
d4e7b28be8
|
cache refactoring
|
2021-01-17 00:18:56 -08:00 |
|
Blaise Tine
|
7c4823e65c
|
fixed GPR reset bug, fixed lsu dup loading, fixed riscv-tests
|
2021-01-11 23:55:09 -08:00 |
|
Blaise Tine
|
e770824d47
|
fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance
|
2021-01-10 20:26:15 -08:00 |
|
Blaise Tine
|
8aea9cbe07
|
minor update
|
2021-01-06 21:39:15 -08:00 |
|
Blaise Tine
|
2b8435471a
|
speeding up simulation using dedicated full dpi-based FPU core
|
2021-01-06 18:44:06 -08:00 |
|
Blaise Tine
|
2d69ca5d67
|
scratchpad optimization for stack access using custom bank offset aligned to stack size
|
2021-01-02 16:00:00 -05:00 |
|
Blaise Tine
|
30d950ada2
|
vx_spawn_warps redesign using opencl's style scheduler
|
2021-01-01 14:13:48 -05:00 |
|
Blaise Tine
|
e4a00dd0d9
|
fixed loader script stack setup
|
2020-12-31 22:37:20 -05:00 |
|
Blaise Tine
|
d44144f72f
|
FPU float<->int conversion optimization
|
2020-12-29 15:37:45 -08:00 |
|
Blaise Tine
|
e83c4638a0
|
FPU area optimization sharing fmadd hard block
|
2020-12-27 17:31:10 -08:00 |
|
Blaise Tine
|
25df233005
|
Adding Altera Stratix 10 support
|
2020-12-27 10:44:57 -08:00 |
|
Blaise Tine
|
b2b8f190dd
|
minor update
|
2020-12-26 14:47:41 -08:00 |
|
Blaise Tine
|
33c431ed44
|
multiplier unit optimization - using fifo for metadata, shift register optimization
|
2020-12-26 11:23:21 -08:00 |
|
Blaise Tine
|
b459192dec
|
critical path optimization - fpga fmax @4c = ~212 mhz
|
2020-12-26 03:28:32 -08:00 |
|
Blaise Tine
|
703a861fe9
|
added support for write-through cache, removed cache snooping support
|
2020-12-23 23:51:02 -08:00 |
|
Blaise Tine
|
d956e268b9
|
adding new performance counters (banks utilization and DRAM bus utilization)
|
2020-12-22 12:33:45 -08:00 |
|
Blaise Tine
|
4b7d871d62
|
allowing partial cache request submissions, io bus support broken
|
2020-12-21 03:53:13 -08:00 |
|
Blaise Tine
|
4bbd7bf408
|
performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
|
2020-12-19 02:45:06 -08:00 |
|
Blaise Tine
|
d5438fd591
|
merging perf counters
|
2020-12-08 21:02:39 -08:00 |
|
Xandy Liu
|
1595ff08e2
|
PERF pipeline stalls and cache
|
2020-12-08 01:14:41 -05:00 |
|
Blaise Tine
|
268ad15098
|
minor update
|
2020-12-06 22:55:17 -08:00 |
|
Blaise Tine
|
d68b32cd60
|
minor update
|
2020-12-06 22:40:27 -08:00 |
|
Blaise Tine
|
1332970636
|
refactoring cores clustering
|
2020-12-06 14:42:12 -08:00 |
|
Blaise Tine
|
b2652527bb
|
data/dram bus refactoring
|
2020-12-06 03:37:22 -08:00 |
|
Blaise Tine
|
478d971389
|
minor update
|
2020-12-03 16:21:20 -08:00 |
|
Blaise Tine
|
0a8f41964d
|
minor update
|
2020-12-03 08:47:03 -08:00 |
|
Blaise Tine
|
b7a724410b
|
update DRAM simulation - reduce the latency of duplicate requests (simulate DRAM cache)
|
2020-12-03 07:30:19 -08:00 |
|
Blaise Tine
|
f68af3bb84
|
using mshr pending request size
|
2020-12-01 00:54:25 -08:00 |
|
Blaise Tine
|
def6a35693
|
shared memory optimization
|
2020-11-29 15:04:31 -08:00 |
|
Blaise Tine
|
b85391389b
|
rename MSRQ to MSHR
|
2020-11-28 17:32:00 -05:00 |
|
Blaise Tine
|
00d7473268
|
build warnings clean
|
2020-11-28 14:59:13 -05:00 |
|