Blaise Tine
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f12be56d7c
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fixed Verilator warnings
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2021-08-13 05:52:43 -04:00 |
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Blaise Tine
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3d19588e57
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bus arbiters refactoring
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2021-07-30 16:00:09 -07:00 |
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Blaise Tine
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ea1e0f201e
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OUTPUT_REG refactoring
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2021-07-23 06:58:37 -07:00 |
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Blaise Tine
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22cf698e69
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minor update
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2021-07-13 05:25:44 -07:00 |
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Blaise Tine
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10e9ee124b
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using onehot multiplexer to reduce critical path
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2021-07-08 00:26:59 -07:00 |
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Blaise Tine
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dc34c5c5bd
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minor update
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2021-07-03 04:47:19 -07:00 |
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Blaise Tine
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93fee18d59
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minor update
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2021-07-01 02:59:44 -07:00 |
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Blaise Tine
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adf033b0aa
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non-cacheable memory address critical paths optimizations
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2021-06-10 12:47:18 -07:00 |
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Blaise Tine
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3f5fd6d394
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using shiftreg-based skid buffers
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2021-02-28 02:20:09 -08:00 |
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Blaise Tine
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073964fdf7
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minor update
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2021-02-12 08:52:06 -08:00 |
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Blaise Tine
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8775f63ec4
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lkg build rollout with 16cores optimization on arria10
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2021-01-24 16:49:22 -08:00 |
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Blaise Tine
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4bbd7bf408
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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
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2020-12-19 02:45:06 -08:00 |
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Blaise Tine
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d5fa82f5e4
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cache req datapath optimizations
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2020-12-08 02:58:08 -08:00 |
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Blaise Tine
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13a5370254
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register file refactoring
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2020-12-05 01:40:50 -08:00 |
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Blaise Tine
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c3ec4c9e90
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minor update
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2020-12-03 09:30:59 -08:00 |
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Blaise Tine
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f3b1069ce8
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adding stream arbiter
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2020-12-03 06:40:23 -08:00 |
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