Commit Graph

59 Commits

Author SHA1 Message Date
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f12be56d7c fixed Verilator warnings 2021-08-13 05:52:43 -04:00
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c2b3aaa7d1 enabling delayed tracing 2021-08-12 20:05:43 -07:00
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cc259f60f6 minor update 2021-08-11 15:39:21 -07:00
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7b8fe11e6a unused variables refactoring 2021-08-05 01:46:26 -07:00
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1ba2a10ad8 minor update 2021-07-25 15:29:15 -07:00
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ea1e0f201e OUTPUT_REG refactoring 2021-07-23 06:58:37 -07:00
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0319283ea7 minor update 2021-07-20 21:42:22 -07:00
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6b641ceb21 minor update 2021-07-17 15:26:04 -07:00
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e0487e4555 minor reset delay fix 2021-07-16 21:31:46 -07:00
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a8248b334c AVS wrapper optimization 2021-07-16 12:58:53 -07:00
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22cf698e69 minor update 2021-07-13 05:25:44 -07:00
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b99fb41d52 minor update 2021-07-08 01:31:12 -07:00
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10e9ee124b using onehot multiplexer to reduce critical path 2021-07-08 00:26:59 -07:00
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86aabbbf5d minor update 2021-06-28 08:00:29 -07:00
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f84c8a0b5d instr_sched => ibuffer 2021-06-27 19:36:43 -07:00
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1ea738ed26 lkg build 2021-06-25 16:28:10 -07:00
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7e0dc81cee minor update 2021-06-23 04:19:13 -07:00
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57143f5889 synthesis optimizations 2021-06-17 16:43:43 -07:00
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6213b1a910 vortex runtime console out implementation 2021-06-15 04:01:44 -04:00
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3cc1190cd7 CSRs I/O refactoring 2021-06-11 03:08:07 -07:00
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cbca7e12c6 removing ebreak signals from public interface 2021-06-10 12:57:44 -07:00
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adf033b0aa non-cacheable memory address critical paths optimizations 2021-06-10 12:47:18 -07:00
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093008fa1e minor update 2021-05-25 09:13:32 -07:00
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6388d87ec5 afu bug fix 2021-05-24 18:06:11 -07:00
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d80e1b28a3 fixes for multi-channel memory support 2021-05-20 05:36:09 -07:00
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7095a46066 minor update 2021-05-18 11:15:36 -07:00
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3e88a71801 minor update 2021-05-06 08:55:46 -07:00
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6107bf8247 minor fix 2021-05-04 11:05:07 -07:00
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8f451aa74c minor update 2021-05-04 08:01:49 -07:00
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bde6a69ea0 adding support for multi-banks memory bus 2021-05-04 07:32:03 -07:00
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bac53e4ae1 minor update 2021-05-02 11:05:49 -07:00
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e40a3feefa minor update 2021-05-01 10:33:24 -07:00
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d504adb236 afu mem controller refactoring 2021-05-01 08:39:52 -07:00
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95f057bc2e fpga build refactoring 2021-04-29 06:17:28 -07:00
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64848788a1 minor update 2021-04-26 20:34:28 -07:00
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8410c49f53 code refactoring: DRAM => MEM renaming 2021-04-26 00:58:48 -07:00
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cad21a4b92 minor update 2021-04-24 01:17:38 -04:00
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4cb98a25a7 enabling 128-bit dram bus 2021-04-24 00:31:27 -04:00
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e85fa9d842 fixed FCVT timing critical path 2021-03-18 13:26:36 -07:00
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062d02ddce Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2021-03-04 20:51:03 -08:00
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8775f63ec4 lkg build rollout with 16cores optimization on arria10 2021-01-24 16:49:22 -08:00
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ed216ab39d minor updates 2021-01-17 13:58:43 -08:00
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fe64c47f60 ccip write fix 2021-01-14 22:49:06 -08:00
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79cc4d98e6 bank deadlock fix 2021-01-13 13:06:07 -08:00
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464c4f4bd8 minor updates 2021-01-12 20:16:59 -08:00
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f18ac24675 afu reset fix 2021-01-12 17:13:47 -08:00
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e770824d47 fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance 2021-01-10 20:26:15 -08:00
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06945533cf fixed l2/l3 caches related bugs 2021-01-09 16:32:55 -08:00
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ba1082249a minor update 2021-01-06 23:30:30 -08:00
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2b8435471a speeding up simulation using dedicated full dpi-based FPU core 2021-01-06 18:44:06 -08:00