felsabbagh3
d31b607e01
Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
2020-03-28 21:43:51 -07:00
felsabbagh3
313a8e3b4b
All cache bugs fixed - Handshaking
2020-03-28 21:43:02 -07:00
Blaise Tine
22be51b0c8
fixed multicore build
2020-03-28 01:40:26 -04:00
felsabbagh3
5dc9493c61
ALL tests passing - handshake
2020-03-27 21:34:49 -07:00
Blaise Tine
e80fa7f233
missing rtl changes from OPAE
2020-03-27 22:37:35 -04:00
Blaise Tine
8bb1f66220
missing rtl changes from OPAE
2020-03-27 22:37:35 -04:00
Blaise Tine
550d96a73c
rtlsim driver works with Vortex!
2020-03-27 21:54:55 -04:00
Blaise Tine
e43f5c8767
rtlsim driver works with Vortex!
2020-03-27 21:54:55 -04:00
Blaise Tine
5d320a9313
fixed multicore build
2020-03-27 21:04:23 -04:00
Blaise Tine
2ed7bd3755
fixed multicore build
2020-03-27 21:04:23 -04:00
Blaise Tine
51fd8974a9
minor build fixes
2020-03-27 20:56:18 -04:00
Blaise Tine
2415199a8c
minor build fixes
2020-03-27 20:56:18 -04:00
Blaise Tine
5a5c9f3981
merging changes from OPAE branch making this branch
2020-03-27 20:19:16 -04:00
Blaise Tine
9b1b8789ac
merging changes from OPAE branch making this branch
2020-03-27 20:19:16 -04:00
felsabbagh3
614797e52f
Migrating fpga_synthesis_temp to main
2020-03-27 13:15:23 -07:00
felsabbagh3
39516a6f98
Migrating fpga_synthesis_temp to main
2020-03-27 13:15:23 -07:00
Blaise Tine
6dc3d0d371
refactor VX_define.v
2020-03-27 13:56:16 -04:00
Blaise Tine
d54ba1e9ae
refactor VX_define.v
2020-03-27 13:56:16 -04:00
Blaise Tine
3df21b6e71
fixed regression bug with Vortex.v model hanging issue
2020-03-27 13:19:11 -04:00
Blaise Tine
4eb8769423
fixed regression bug with Vortex.v model hanging issue
2020-03-27 13:19:11 -04:00
Blaise Tine
985b01cb99
adding back build_config target dependency
2020-03-27 12:41:03 -04:00
Blaise Tine
073173067f
adding back build_config target dependency
2020-03-27 12:41:03 -04:00
Blaise Tine
8763adf7bc
update
2020-03-26 04:19:53 -04:00
Blaise Tine
50829e522b
update
2020-03-26 04:19:53 -04:00
Blaise Tine
a82dd9387d
refactoring RTL simulator and Makefile
2020-03-26 04:14:36 -04:00
Blaise Tine
3252d52694
refactoring RTL simulator and Makefile
2020-03-26 04:14:36 -04:00
wgulian3
3b74f071a7
Generate define overrides based on env vars for C and Verilog.
...
gen_config.py has two main jobs. First it parses env vars for anything starting with V_ and treats this as an override define. These defines are inserted into the emitted .h and .v headers with correct syntax for C and Verilog preprocessors, respectively. Second, it translates VX_define.v including all conditional definition rules into a C header. This way, all values defined in VX_define.v can also be referenced in corresponding runtime or Verilator code.
2020-03-26 04:08:43 -04:00
wgulian3
f126a23114
Generate define overrides based on env vars for C and Verilog.
...
gen_config.py has two main jobs. First it parses env vars for anything starting with V_ and treats this as an override define. These defines are inserted into the emitted .h and .v headers with correct syntax for C and Verilog preprocessors, respectively. Second, it translates VX_define.v including all conditional definition rules into a C header. This way, all values defined in VX_define.v can also be referenced in corresponding runtime or Verilator code.
2020-03-26 04:08:43 -04:00
wgulian3
33d8c507df
Remove VX_define.h and *_synth and runtime/config.h
2020-03-26 04:07:17 -04:00
wgulian3
123fb17723
Remove VX_define.h and *_synth and runtime/config.h
2020-03-26 04:07:17 -04:00
Blaise Tine
8fd742edd8
fixed Modelsim build errors
2020-03-26 03:56:44 -04:00
Blaise Tine
acafcceb94
fixed Modelsim build errors
2020-03-26 03:56:44 -04:00
Blaise Tine
9621acff5b
fixed Modelsim build errors
2020-03-26 03:54:23 -04:00
Blaise Tine
8aa2d74714
fixed Modelsim build errors
2020-03-26 03:54:23 -04:00
Blaise Tine
a7eb9a0c38
code refactoring
2020-03-26 03:20:46 -04:00
Blaise Tine
07c52d8729
code refactoring
2020-03-26 03:20:46 -04:00
Blaise Tine
4626389ee2
code refactoring
2020-03-26 01:41:01 -04:00
Blaise Tine
bf3d1fb5a2
code refactoring
2020-03-26 01:41:01 -04:00
felsabbagh3
4e6de0dc38
Fixed most of the cache issues, mat_add left
2020-03-22 15:59:45 -07:00
felsabbagh3
5372c07b01
Fixed most of the cache issues, mat_add left
2020-03-22 15:59:45 -07:00
felsabbagh3
d146070275
Fix for Single-Threaded
2020-03-22 14:44:46 -07:00
felsabbagh3
82ea79c680
Fix for Single-Threaded
2020-03-22 14:44:46 -07:00
wgulian3
902aa685b1
Add threaded -O3 build mode
2020-03-21 17:23:40 -04:00
wgulian3
10ebfd7e24
Add threaded -O3 build mode
2020-03-21 17:23:40 -04:00
wgulian3
1c82f9a11d
revert saxpy change and fix stage_1_cycles not working
2020-03-20 04:49:02 -04:00
wgulian3
f565d47844
revert saxpy change and fix stage_1_cycles not working
2020-03-20 04:49:02 -04:00
wgulian3
05b7ffff12
Add modified RTL files for parameterized builds with VX_define_synth.v
2020-03-20 04:04:15 -04:00
wgulian3
5b3df797a4
Add modified RTL files for parameterized builds with VX_define_synth.v
2020-03-20 04:04:15 -04:00
felsabbagh3
65f3ced608
Fixed no L3 Verilator issues
2020-03-13 15:11:20 -07:00
felsabbagh3
ff2fc5fa43
Fixed no L3 Verilator issues
2020-03-13 15:11:20 -07:00
