Blaise Tine
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369c2c625c
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synthesis fixes
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2020-03-05 06:58:51 -05:00 |
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codetector
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e901fb6a3a
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remove async reset for FPGA synthesis
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2020-02-19 23:19:05 -05:00 |
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wgulian3
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8d20b52ea2
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Cleanup imports of VX_define
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2020-02-04 10:57:32 -05:00 |
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wgulian3
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e9cdc6e5af
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SystemVerilog tweaks to appease Quartus and make Quartus synthesis work
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2020-01-24 06:10:24 -05:00 |
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Lyons, Ethan Tyler
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b748a7665d
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Synthesis Compatible
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2019-11-21 21:41:41 -05:00 |
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fares
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53c78b905a
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Switched to g++
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2019-11-16 12:23:59 -05:00 |
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felsabbagh3
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7ed88ce4c1
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Fixed AA d_cache sizing errors
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2019-11-11 15:20:58 -05:00 |
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felsabbagh3
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92e88a7bb2
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Fixed cache meta
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2019-11-10 15:38:39 -05:00 |
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felsabbagh3
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31de18c328
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Changed tb
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2019-11-10 15:06:06 -05:00 |
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felsabbagh3
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fbf708e419
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Started simX
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2019-11-10 01:21:09 -05:00 |
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felsabbagh3
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ea7bd485ca
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Icache/Dcache finally done + configurability tested:
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2019-11-09 00:03:15 -05:00 |
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felsabbagh3
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8b81989bfd
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Before way logic change
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2019-11-08 18:16:40 -05:00 |
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Lyons, Ethan Tyler
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6c4cd2468f
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Add files via upload
ICache_In_Place
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2019-11-08 10:55:35 -05:00 |
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felsabbagh3
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5d5ad9c4ec
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FIXED BUGS
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2019-11-07 13:54:46 -05:00 |
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felsabbagh3
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58a9140f08
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Before evict_wb_old removal
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2019-11-07 13:27:38 -05:00 |
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Savan Roshan
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e4ee2a9cbd
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Parameterization working
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2019-11-07 00:14:46 -05:00 |
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Savan Roshan
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cb1bf65017
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Parameterization working
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2019-11-06 11:12:27 -05:00 |
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Savan Roshan
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3a71a2ebdb
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Fixed bugs in parameterization
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2019-11-06 01:09:30 -05:00 |
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Savan Roshan
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8468e7d4d9
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Added prefix DCACHE_
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2019-11-05 08:33:38 -05:00 |
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Savan Roshan
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1db160a289
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Fixed parameterization
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2019-11-04 14:32:02 -05:00 |
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Savan Roshan
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8264339853
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Added Parameterization
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2019-11-04 13:20:34 -05:00 |
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felsabbagh3
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bbb2373919
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Intrinsics: tests for TMC+Control Divergence
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2019-11-01 21:53:37 -04:00 |
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Savan Roshan
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2b9f6f3d0b
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Fixed eviction_wb
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2019-11-01 00:39:02 -04:00 |
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felsabbagh3
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7863175233
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Set associative bank working
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2019-10-30 14:57:20 -04:00 |
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Lingjun Zhu
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b6558714ca
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Finished synthesis with all memory but no optimization
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2019-10-28 16:18:11 -04:00 |
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Lingjun Zhu
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0b30b3a35f
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Resolved most connection error, expect QA of rf2_256x19_wm0 in VX_cache_data
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2019-10-28 15:06:23 -04:00 |
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felsabbagh3
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a8d063e9ad
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Synthesis Cleanup 1
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2019-10-28 13:43:12 -04:00 |
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felsabbagh3
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88eab9e746
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Removed dependancy on
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2019-10-27 22:30:32 -04:00 |
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felsabbagh3
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715982cca7
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Modelsim Working + Simulating + dumping - Some bugs
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2019-10-27 03:36:02 -04:00 |
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felsabbagh3
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1181af1df2
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Modelsim basic sim
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2019-10-26 00:34:57 -04:00 |
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felsabbagh3
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820007ae80
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NUM_REQ
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2019-10-25 13:46:31 -04:00 |
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felsabbagh3
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c85c01e082
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Parametized cache
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2019-10-25 13:36:06 -04:00 |
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felsabbagh3
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89d0390965
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CACHE FINALLY WORKING
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2019-10-25 04:01:23 -04:00 |
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felsabbagh3
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01efe02e8b
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CACHE WORKING just needs lb/sb
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2019-10-25 03:03:09 -04:00 |
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felsabbagh3
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1e648c5819
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FIxed first circular issue
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2019-10-24 10:38:04 -04:00 |
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felsabbagh3
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de8de00f6e
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Finished cache not tested
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2019-10-23 19:07:26 -04:00 |
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felsabbagh3
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6340ffcc2a
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new cache states
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2019-10-23 15:07:14 -04:00 |
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felsabbagh3
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1645a04b1d
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Fixed SM + added def SYN
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2019-10-22 15:56:30 -04:00 |
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felsabbagh3
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9d8273afe4
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Finished Cache Integration
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2019-10-22 06:02:08 -04:00 |
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