Blaise Tine
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e92c4b6774
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enable rtl sim dram stalls
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2020-03-31 02:38:18 -04:00 |
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felsabbagh3
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ba8bc95c90
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Newlib update
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2020-03-30 23:08:38 -07:00 |
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felsabbagh3
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bcf894b581
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Demo SOC W=8, T=4 Passing
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2020-03-30 22:17:38 -07:00 |
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felsabbagh3
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66a837b0df
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SOC only 2 errors
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2020-03-30 21:28:40 -07:00 |
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felsabbagh3
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88f2ad53d0
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Fixed simulator includes
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2020-03-30 16:43:26 -07:00 |
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Blaise Tine
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f6eb5dfbae
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refactor RTL sim, added DRAM stalls support
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2020-03-30 04:13:19 -04:00 |
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felsabbagh3
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638625184f
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-03-29 23:46:44 -07:00 |
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felsabbagh3
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ff2b8dba12
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Fixed req_addr width
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2020-03-29 23:46:38 -07:00 |
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Blaise Tine
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0f39d0fcbd
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-03-30 01:53:53 -04:00 |
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Blaise Tine
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2eb19e23c2
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refactor RTL simulator
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2020-03-30 01:53:34 -04:00 |
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felsabbagh3
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ccc65a06fe
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-03-29 21:22:08 -07:00 |
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felsabbagh3
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36895d6e7c
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Fixed miss_add on for snoop replays
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2020-03-29 21:21:53 -07:00 |
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Blaise Tine
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2d198a32c7
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update
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2020-03-29 23:18:26 -04:00 |
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felsabbagh3
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94cc2c10b1
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Snoops shouldn't send fill requests
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2020-03-29 19:16:00 -07:00 |
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felsabbagh3
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e31b2d6d7e
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Fixed pulling signals from different stages
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2020-03-29 18:17:01 -07:00 |
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felsabbagh3
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d31116d584
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Uses use_wb_valid instead of wb_req to include snoops
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2020-03-29 17:59:10 -07:00 |
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felsabbagh3
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71aae3e0a9
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..
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2020-03-29 17:28:57 -07:00 |
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felsabbagh3
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f96d77d75e
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Mismatched vs matched
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2020-03-29 17:18:57 -07:00 |
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felsabbagh3
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a499bcd718
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Added extra signals for debugging
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2020-03-29 17:04:17 -07:00 |
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felsabbagh3
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95ee66f25a
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Fixed Snoop Invalidate Logic
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2020-03-29 16:44:14 -07:00 |
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felsabbagh3
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73390b9f58
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b/unb error
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2020-03-29 16:09:48 -07:00 |
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felsabbagh3
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0a88c97485
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Another reset issue...
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2020-03-29 16:06:13 -07:00 |
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felsabbagh3
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b99ba2c413
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Removed scheduler_empty qualifier
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2020-03-29 15:24:50 -07:00 |
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felsabbagh3
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eb6e0cee43
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Fixing a bug in a fix...
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2020-03-29 13:52:22 -07:00 |
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felsabbagh3
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cd418a1f96
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Mrvq stopping reqq popping added to avoid mrvq full deadlock
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2020-03-29 13:19:06 -07:00 |
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felsabbagh3
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f43a9ad1a6
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Added proper resetting to cache
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2020-03-29 10:57:32 -07:00 |
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Blaise Tine
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3a23e05a88
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-03-29 05:24:48 -04:00 |
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Blaise Tine
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ce0cc44d11
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update
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2020-03-29 05:24:40 -04:00 |
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felsabbagh3
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2c75b7e800
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-03-29 02:11:23 -07:00 |
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felsabbagh3
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efac643c66
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Added Proper Handshaking to Everything and Fixed a Couple of Bugs
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2020-03-29 02:11:14 -07:00 |
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Blaise Tine
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ede41dff1b
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-03-29 01:17:32 -04:00 |
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Blaise Tine
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c57de94b5c
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minor update
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2020-03-29 01:17:09 -04:00 |
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felsabbagh3
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d31b607e01
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-03-28 21:43:51 -07:00 |
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felsabbagh3
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313a8e3b4b
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All cache bugs fixed - Handshaking
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2020-03-28 21:43:02 -07:00 |
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Blaise Tine
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002d8fbec9
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minor update
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2020-03-29 00:40:02 -04:00 |
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Blaise Tine
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c8a6470595
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redesigned driver demo, fixed startup code, removed --cpu from simx,
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2020-03-29 00:38:17 -04:00 |
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Blaise Tine
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2d5cf89e00
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update
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2020-03-28 02:40:38 -04:00 |
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Blaise Tine
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17625e7709
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update
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2020-03-28 01:43:26 -04:00 |
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Blaise Tine
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22be51b0c8
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fixed multicore build
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2020-03-28 01:40:26 -04:00 |
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Blaise Tine
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cff762c435
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adding opencl runtime and compiler tools
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2020-03-28 00:35:54 -04:00 |
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felsabbagh3
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5dc9493c61
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ALL tests passing - handshake
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2020-03-27 21:34:49 -07:00 |
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Blaise Tine
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f7e0d1e491
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missing runtime changes from OPAE
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2020-03-27 22:51:54 -04:00 |
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Blaise Tine
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96e960fa69
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missing runtime changes from OPAE
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2020-03-27 22:51:54 -04:00 |
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Blaise Tine
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89d5bfbef1
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missing simX changes from OPAE
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2020-03-27 22:44:16 -04:00 |
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Blaise Tine
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f3889f8744
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missing simX changes from OPAE
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2020-03-27 22:44:16 -04:00 |
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Blaise Tine
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e80fa7f233
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missing rtl changes from OPAE
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2020-03-27 22:37:35 -04:00 |
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Blaise Tine
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8bb1f66220
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missing rtl changes from OPAE
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2020-03-27 22:37:35 -04:00 |
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Blaise Tine
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550d96a73c
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rtlsim driver works with Vortex!
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2020-03-27 21:54:55 -04:00 |
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Blaise Tine
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e43f5c8767
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rtlsim driver works with Vortex!
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2020-03-27 21:54:55 -04:00 |
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Blaise Tine
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5d320a9313
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fixed multicore build
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2020-03-27 21:04:23 -04:00 |
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