Hansung Kim
e2d3d93dea
Properly initialize DCR in wrapper code
2023-11-16 17:59:57 -08:00
Hansung Kim
963c2765d9
Move force-include of gpu_pkg to non-cache modules
2023-11-15 22:02:44 -08:00
Hansung Kim
448a253af3
Add Verilog wrapper module for VX_core
2023-11-15 20:09:53 -08:00
Hansung Kim
bbacf9a25e
Remove verilated vpi code, add missing includes for C++
...
Vortex rtlsim defines sim_trace_enabled... functions in the Verilated
C++ code for use in dpi_trace, which we don't need.
2023-11-15 20:06:58 -08:00
Hansung Kim
d9cb14d6e4
Fix include path in rvfloats.cpp to work with Chisel addResources
...
addResource() in Chisel flattens everything to gen-collateral/ dir, so
cannot use relative path for includes.
2023-11-15 20:06:18 -08:00
Hansung Kim
7e0b63a3b3
Change result type for dpi calls from wire -> reg
...
VCS requires the output of the dpi calls to be of a type that can come
at the LHS of a procedural assignment, i.e. reg type. Seems to be a
different requirement from Verilator.
2023-11-15 19:26:12 -08:00
Hansung Kim
d2d7ee61bb
Define SIMULATION for VCS in VX_platform.vh
2023-11-15 19:14:58 -08:00
Hansung Kim
512fc0da1c
Copy VX_platform macros for VCS from VERILATOR
2023-11-15 00:20:18 -08:00
Hansung Kim
20a9e6d102
Force include VX_gpu_pkg as compile order workaround
...
addResource() calls in Chisel BlackBox does not preserve order of the
files being included; the actual compile order for these files are
re-arranged to be in alphabetical order.
Therefore, while VX_gpu_pkg.sv has to be compiled before all the other
modules because it holds the top-level package definition, that order
cannot be ensured from Chisel. As a hacky workaround, simply `include
this file in some of the sv files whose name starts earlier than
VX_gpu_pkg in lexicographical order.
2023-11-14 23:00:43 -08:00
Blaise Tine
64dc5e1667
Merge branch 'develop'
2023-11-10 02:57:42 -08:00
Blaise Tine
c1e168fdbe
Vortex 2.0 changes:
...
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
minor update
minor update
minor update
minor update
minor update
minor update
cleanup
cleanup
cache bindings and memory perf refactory
minor update
minor update
hw unit tests fixes
minor update
minor update
minor update
minor update
minor update
minor udpate
minor update
minor update
minor update
minor update
minor update
minor update
minor update
minor updates
minor updates
minor update
minor update
minor update
minor update
minor update
minor update
minor updates
minor updates
minor updates
minor updates
minor update
minor update
2023-11-10 02:47:05 -08:00
Blaise Tine
6e93787e59
minor update
2023-11-06 00:16:24 -08:00
Blaise Tine
e0becb1599
minor update
2023-11-05 20:03:31 -08:00
Blaise Tine
d13c5f2986
hw unit tests fixes
2023-11-05 18:51:31 -08:00
Blaise Tine
1fd5a95f5a
minor update
2023-11-03 18:04:05 -04:00
Blaise Tine
9f1f1ecaa3
minor update
2023-11-03 08:36:28 -04:00
Blaise Tine
c9e6518e05
cache bindings and memory perf refactory
2023-11-03 08:18:18 -04:00
Blaise Tine
69f9ae778d
cleanup
2023-11-03 08:12:03 -04:00
Blaise Tine
970cbf066a
cleanup
2023-11-03 08:09:59 -04:00
Blaise Tine
1c100c4cf5
minor update
2023-10-22 23:31:58 -07:00
Blaise Tine
cb7d6b964c
minor update
2023-10-22 02:25:34 -07:00
Blaise Tine
8cf833b7eb
minor update
2023-10-21 19:12:07 -07:00
Blaise Tine
8fe373891f
minor update
2023-10-21 17:55:29 -07:00
Blaise Tine
3cacb4f80f
minor update
2023-10-20 02:21:20 -07:00
Blaise Tine
65ca0fff3a
minor update
2023-10-20 00:48:05 -07:00
Blaise Tine
d47cccc157
Vortex 2.0 changes:
...
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
2023-10-19 20:51:22 -07:00
Blaise Tine
d69a64c32c
minor update
2023-05-16 04:59:01 -04:00
Blaise Tine
b9cda8fca7
minor update
2023-05-15 20:19:14 -04:00
Blaise Tine
1136c664f1
minor update
2023-05-15 19:51:20 -04:00
Blaise Tine
1243848963
minor update
2023-05-15 19:13:45 -04:00
Blaise Tine
dce5e79f65
toolchain update
2023-05-15 18:53:24 -04:00
tinebp
88ed687557
Update .travis.yml
2022-09-30 04:19:53 -04:00
tinebp
ebff870d54
Update .travis.yml
2022-09-30 03:09:35 -04:00
tinebp
d802defd6c
Update .travis.yml
2022-09-30 01:44:54 -04:00
tinebp
ff4c24657e
Update README.md
2022-09-29 21:05:35 -04:00
Blaise Tine
e1b666cb93
minor update
2022-07-14 08:55:09 -04:00
Blaise Tine
da834a28df
adding support for TLS global variables
2022-07-14 06:03:02 -04:00
Blaise Tine
77002dd06a
minor updates
2022-02-05 20:52:23 -05:00
Blaise Tine
76481bc794
minor update
2022-02-05 20:41:44 -05:00
Blaise Tine
5a5f1ad3fe
minor update
2022-02-05 18:03:38 -05:00
Blaise Tine
2277e3c878
minor update
2022-02-05 17:59:58 -05:00
Blaise Tine
1bd25acb0b
cmov
2022-02-05 17:58:12 -05:00
Blaise Tine
d297351211
simx64 bug fix
2022-02-05 17:13:16 -05:00
Blaise Tine
2fd93e1d89
Merge branch 'staging' of https://github.com/vortexgpgpu/vortex
2022-02-05 16:12:52 -05:00
tinebp
a5ab68d9df
Merge pull request #42 from SantoshSrivatsan24/staging
...
Staging
2022-02-05 14:55:49 -05:00
Santosh Srivatsan
1b5b7a3cba
Modified travis.yml
2022-02-05 14:45:21 -05:00
Santosh Srivatsan
6dd6a88c12
Modified regression64.sh
2022-02-05 14:37:05 -05:00
Santosh Srivatsan
09833fdfb1
Fixed merge conflict
2022-02-05 14:34:36 -05:00
tinebp
eacdb63454
Merge pull request #41 from SantoshSrivatsan24/staging
...
Staging
2022-02-05 14:25:17 -05:00
Santosh Srivatsan
1c781c78c0
Minor bug fix
2022-02-05 14:17:56 -05:00
