 felsabbagh3
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457e8644f3
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Added Snoop Invalidate/Writeback Req type
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2020-03-05 01:30:16 -08:00 |
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felsabbagh3
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7222cdd199
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Added Snoop Invalidate/Writeback Req type
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2020-03-05 01:30:16 -08:00 |
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felsabbagh3
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e0620a6f6a
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Added fill_invalidator
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2020-03-04 23:55:02 -08:00 |
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felsabbagh3
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c257c0578e
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Added fill_invalidator
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2020-03-04 23:55:02 -08:00 |
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felsabbagh3
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b038bdb491
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New Cache Design Passing All Tests
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2020-03-04 23:24:32 -08:00 |
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felsabbagh3
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a86a403ca9
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New Cache Design Passing All Tests
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2020-03-04 23:24:32 -08:00 |
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felsabbagh3
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b0b9b8238e
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Passing some cases
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2020-03-04 04:05:54 -08:00 |
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felsabbagh3
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aa1a0ee376
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Passing some cases
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2020-03-04 04:05:54 -08:00 |
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felsabbagh3
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8f001ac6f2
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Added All Interfaces
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2020-03-03 22:48:49 -08:00 |
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felsabbagh3
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d8e25045be
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Added All Interfaces
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2020-03-03 22:48:49 -08:00 |
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felsabbagh3
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73cecd3866
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Added Core Interface
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2020-03-03 22:14:56 -08:00 |
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felsabbagh3
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01ae6ffafe
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Added Core Interface
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2020-03-03 22:14:56 -08:00 |
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felsabbagh3
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57a96e02b1
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Fixed some other timing issues
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2020-03-03 21:15:44 -08:00 |
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felsabbagh3
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58db00f555
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Fixed some other timing issues
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2020-03-03 21:15:44 -08:00 |
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felsabbagh3
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08986bf1dc
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Fixed incorrect valid and'ing in execute
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2020-03-03 20:57:20 -08:00 |
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felsabbagh3
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25b6dbdfa8
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Fixed incorrect valid and'ing in execute
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2020-03-03 20:57:20 -08:00 |
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felsabbagh3
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a47f7c11ec
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Finished cache, dram imp + interfaces left
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2020-03-03 19:42:33 -08:00 |
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felsabbagh3
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733d00aba9
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Finished cache, dram imp + interfaces left
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2020-03-03 19:42:33 -08:00 |
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felsabbagh3
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8ece8d8893
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Fixed miss reserv to support ST->LD sequences
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2020-03-03 17:04:39 -08:00 |
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felsabbagh3
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e2e053ff7b
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Fixed miss reserv to support ST->LD sequences
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2020-03-03 17:04:39 -08:00 |
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felsabbagh3
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80af320fdb
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Before fixing miss rsrv for ST->LD sequences
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2020-03-03 16:57:05 -08:00 |
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felsabbagh3
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b150327ca9
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Before fixing miss rsrv for ST->LD sequences
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2020-03-03 16:57:05 -08:00 |
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felsabbagh3
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361fc2c3fe
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Finished st0
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2020-03-03 02:49:30 -08:00 |
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felsabbagh3
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8784b09b18
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Finished st0
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2020-03-03 02:49:30 -08:00 |
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felsabbagh3
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3a970bbe7b
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Connected cache to bank
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2020-03-02 23:24:17 -08:00 |
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felsabbagh3
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8c6284f627
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Connected cache to bank
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2020-03-02 23:24:17 -08:00 |
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felsabbagh3
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fc5621cd1d
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Everything except bank internals
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2020-03-02 23:08:54 -08:00 |
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felsabbagh3
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f6cc05eaa2
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Everything except bank internals
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2020-03-02 23:08:54 -08:00 |
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felsabbagh3
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abca2f7abb
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Modified Scheduler to be mask based (allows thread granuility writebacks) + Fixed all LW and SW unit test errors errors
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2020-03-01 22:27:18 -08:00 |
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felsabbagh3
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d78338c7d4
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Modified Scheduler to be mask based (allows thread granuility writebacks) + Fixed all LW and SW unit test errors errors
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2020-03-01 22:27:18 -08:00 |
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felsabbagh3
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6bf25b5b78
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+Added icache stage -- 3rd case of AUIPC os broken?
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2020-03-01 18:01:02 -08:00 |
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felsabbagh3
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f98f5c414d
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+Added icache stage -- 3rd case of AUIPC os broken?
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2020-03-01 18:01:02 -08:00 |
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wgulian3
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23aabbf01d
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Make ALU div/mul pipelines longer and support logic element multiplication mode for better long pipeline performance
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2020-02-22 20:16:13 -05:00 |
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wgulian3
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ca61801199
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Make ALU div/mul pipelines longer and support logic element multiplication mode for better long pipeline performance
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2020-02-22 20:16:13 -05:00 |
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wgulian3
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b2afe526fe
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Update multiply for not SYN_FUNC
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2020-02-21 23:20:04 -05:00 |
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wgulian3
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a099cb25cf
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Update multiply for not SYN_FUNC
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2020-02-21 23:20:04 -05:00 |
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wgulian3
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f2c0453702
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Add multi-cycle compat module and use it in ALU
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2020-02-21 22:08:09 -05:00 |
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wgulian3
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2c40874cc5
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Add multi-cycle compat module and use it in ALU
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2020-02-21 22:08:09 -05:00 |
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wgulian3
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83d1f54fcf
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fix shared mem ram inference
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2020-02-20 15:59:23 -05:00 |
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wgulian3
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e145b8078c
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fix shared mem ram inference
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2020-02-20 15:59:23 -05:00 |
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wgulian3
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55d722364d
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Merge branch 'fpga_synthesis' into fix_cache_m10k
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2020-02-20 02:36:39 -05:00 |
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wgulian3
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2d3b790324
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Merge branch 'fpga_synthesis' into fix_cache_m10k
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2020-02-20 02:36:39 -05:00 |
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codetector
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e82e29c855
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remove async reset for FPGA synthesis
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2020-02-19 23:19:05 -05:00 |
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codetector
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e901fb6a3a
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remove async reset for FPGA synthesis
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2020-02-19 23:19:05 -05:00 |
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wgulian3
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de85cfd296
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fix clean build with makefile
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2020-02-19 17:33:51 -05:00 |
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Codetector
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072c89c433
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Merge branch 'fpga_synthesis' into fix_cache_m10k
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2020-02-19 16:03:23 -05:00 |
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Codetector
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1a29007bc7
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Merge branch 'fpga_synthesis' into fix_cache_m10k
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2020-02-19 16:03:23 -05:00 |
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wgulian3
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5dadeffac8
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fix project.tcl
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2020-02-19 14:20:58 -05:00 |
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wgulian3
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3b60c10460
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Merge branch 'fpga_synthesis' of github.gatech.edu:casl/Vortex into fpga_synthesis
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2020-02-19 01:04:55 -05:00 |
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wgulian3
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3423e3189f
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Fix e2e building issues and increase division pipeline length
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2020-02-19 01:04:48 -05:00 |
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