Blaise Tine
|
dc7efbcfb4
|
pipeline refactoring
|
2020-07-21 05:22:47 -04:00 |
|
Blaise Tine
|
577a5791dc
|
pipeline refactoring
|
2020-07-20 08:04:04 -04:00 |
|
Blaise Tine
|
25f66e6490
|
pipeline refactoring
|
2020-07-19 05:03:47 -04:00 |
|
Blaise Tine
|
bdfacf709c
|
yosys synthesis refactoring
|
2020-07-10 18:56:41 -04:00 |
|
Blaise Tine
|
77c3b2d45f
|
lsu_unit refactoring to reduce critical path
|
2020-07-10 11:23:34 -07:00 |
|
Blaise Tine
|
582a00d690
|
adding OPAE CSR support
|
2020-06-30 10:05:57 -07:00 |
|
felsabbagh3
|
14e4fd95b7
|
Don't allow snrq scheduling if there's a valid reqq entry (Event if it can't be scheduled)
|
2020-06-29 00:03:36 -07:00 |
|
felsabbagh3
|
21566cdcd7
|
Fixed Single Core with Optimizations
|
2020-06-28 19:38:36 -07:00 |
|
felsabbagh3
|
567376971e
|
Added dram_fill_req_fast which is used to stall bank pipeline
|
2020-06-28 15:22:36 -07:00 |
|
felsabbagh3
|
ffb760cf73
|
Optimized cache writeback path by 1) VX_fair_arbiter and 2) Added a wb register between LSU and WB arbiter
|
2020-06-28 14:27:47 -07:00 |
|
felsabbagh3
|
c95d3cb22b
|
Added cache critical path optimizations
|
2020-06-27 16:12:22 -07:00 |
|
Blaise Tine
|
baf7d3bb92
|
minor update
|
2020-06-27 17:46:45 -04:00 |
|
Blaise Tine
|
bc0c65dce7
|
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
|
2020-06-27 13:56:44 -07:00 |
|
Blaise Tine
|
8302641510
|
fpga fixes
|
2020-06-27 14:03:20 -07:00 |
|
Blaise Tine
|
8a306de02d
|
runtime static library
|
2020-06-27 14:13:13 -04:00 |
|
Blaise Tine
|
0a01385a2c
|
few updates
|
2020-06-23 09:28:24 -07:00 |
|
Blaise Tine
|
d3440de403
|
round robin arbiter + auto buffered queue + fixed dcache arbiter
|
2020-06-20 17:56:04 -04:00 |
|
Blaise Tine
|
68d9fc9a75
|
driver basic test and demo test refactoring
|
2020-06-19 09:12:07 -07:00 |
|
Blaise Tine
|
d6b0ef2b3c
|
scope refactoring + snoop invalidate
|
2020-06-12 00:04:31 -07:00 |
|
Blaise Tine
|
c4f2488dbe
|
Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
t
# the commit.
|
2020-06-04 15:44:40 -07:00 |
|
Blaise Tine
|
4e0e710182
|
OPAE rtl fixes
|
2020-06-04 15:44:03 -07:00 |
|
Blaise Tine
|
171d46b501
|
fix l2 cache issues
|
2020-06-04 18:34:14 -04:00 |
|
Blaise Tine
|
ea890b457d
|
fixed msrq regression
|
2020-06-03 17:22:24 -04:00 |
|
Blaise Tine
|
04fc34b848
|
minor update
|
2020-06-03 03:05:45 -07:00 |
|
Blaise Tine
|
9b186dcc6e
|
fixed L2 cache
|
2020-06-02 05:32:50 -07:00 |
|
Blaise Tine
|
e01c411b20
|
opae rtl fixes
|
2020-06-01 23:06:13 -07:00 |
|
Blaise Tine
|
16d5a8a09c
|
opae rtl fixes
|
2020-05-31 14:51:42 -07:00 |
|
Blaise Tine
|
6a3b237054
|
minor update
|
2020-05-29 00:57:59 -04:00 |
|
felsabbagh3
|
033381ab6f
|
Force correct word selection when BANK_LINE_WORD=1
|
2020-05-28 20:39:39 -07:00 |
|
Blaise Tine
|
33b273b204
|
Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
|
2020-05-28 18:34:25 -04:00 |
|
Blaise Tine
|
b930a822ad
|
minor updates
|
2020-05-28 18:34:03 -04:00 |
|
Blaise Tine
|
611ceb000a
|
fixed warp_sched lock bug
|
2020-05-28 08:52:20 -04:00 |
|
Blaise Tine
|
9e5885b820
|
adding dram writeenable support + scheduler bug fixes
|
2020-05-27 19:00:23 -04:00 |
|
Blaise Tine
|
61231cd2af
|
OPAE rtl fixes
|
2020-05-24 02:42:56 -07:00 |
|
Blaise Tine
|
a9f896b4f3
|
fixed snoop forwarding bug and single bank support
|
2020-05-24 04:29:43 -04:00 |
|
Blaise Tine
|
47ed6b18ff
|
Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
|
2020-05-24 01:37:55 -04:00 |
|
felsabbagh3
|
a1e9b512b0
|
Added mrvq_recover_ready_state_st2 to optimize fills sent
|
2020-05-23 21:47:51 -07:00 |
|
felsabbagh3
|
0cd9bd689e
|
Added schedule_ptr to mrvq for speculative pops
|
2020-05-23 21:36:57 -07:00 |
|
Blaise Tine
|
3a9e79d979
|
revert byte_enable tag structure
|
2020-05-23 22:23:25 -04:00 |
|
Blaise Tine
|
c54fa50715
|
fixed snoop forwarder dequue to support out of order responses
|
2020-05-23 20:19:54 -04:00 |
|
Blaise Tine
|
6882d88a62
|
removed fill_invalidator (not needed anymore)
|
2020-05-23 19:24:52 -04:00 |
|
Blaise Tine
|
f3b21aab8f
|
remove unsued cache parameter LLVQ_SIZE
|
2020-05-23 00:33:51 -04:00 |
|
Blaise Tine
|
b02fc14da6
|
fill invalifator fix + refactoring
|
2020-05-21 20:38:55 -07:00 |
|
Blaise Tine
|
3c8620e770
|
minor update
|
2020-05-21 14:51:56 -04:00 |
|
Blaise Tine
|
cf22ef2bf3
|
minor update
|
2020-05-21 13:42:08 -04:00 |
|
felsabbagh3
|
7e091b53f8
|
Added valid_table in scheduler and removed rename_table on reset
|
2020-05-20 23:02:41 -07:00 |
|
Blaise Tine
|
7e5fed3ec1
|
Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
|
2020-05-20 18:27:20 -04:00 |
|
Blaise Tine
|
72d54c749c
|
fixed cache msrq reset logic
|
2020-05-20 18:11:31 -04:00 |
|
Blaise Tine
|
e1b4862f85
|
minor update
|
2020-05-20 14:14:29 -07:00 |
|
Blaise Tine
|
cefd0d85af
|
rtl refactoring
|
2020-05-20 16:59:14 -04:00 |
|