felsabbagh3
|
7863175233
|
Set associative bank working
|
2019-10-30 14:57:20 -04:00 |
|
Lingjun Zhu
|
3609742707
|
Finished synthesis at 1GHz, cell count increases to 1870k
|
2019-10-29 11:33:23 -04:00 |
|
Lingjun Zhu
|
3c6f0b5d15
|
Included the SDC and DDC files
|
2019-10-28 17:24:19 -04:00 |
|
Lingjun Zhu
|
fa5b476874
|
Added the synthesis netlist
|
2019-10-28 17:11:15 -04:00 |
|
Lingjun Zhu
|
0d8a7be5c6
|
Finished synthesis with optimization
|
2019-10-28 17:10:30 -04:00 |
|
Lingjun Zhu
|
b6558714ca
|
Finished synthesis with all memory but no optimization
|
2019-10-28 16:18:11 -04:00 |
|
Lingjun Zhu
|
0b30b3a35f
|
Resolved most connection error, expect QA of rf2_256x19_wm0 in VX_cache_data
|
2019-10-28 15:06:23 -04:00 |
|
Lingjun Zhu
|
50d567d70c
|
Removed unnessary Verilog files, linked memory tech files, having problem with memory instatiation
|
2019-10-28 14:49:55 -04:00 |
|
felsabbagh3
|
557c987bb0
|
Updated files list
|
2019-10-28 14:29:07 -04:00 |
|
felsabbagh3
|
28ee1d3c36
|
Sucess Synthesis - Finding db
|
2019-10-28 13:52:49 -04:00 |
|
felsabbagh3
|
a8d063e9ad
|
Synthesis Cleanup 1
|
2019-10-28 13:43:12 -04:00 |
|
felsabbagh3
|
8013708a5b
|
Added fsyn for my synthesis
|
2019-10-27 22:16:57 -04:00 |
|
felsabbagh3
|
6fda88b68f
|
Modelsim Makefile compile + simulate - DPI
|
2019-10-26 19:01:49 -04:00 |
|
felsabbagh3
|
de8de00f6e
|
Finished cache not tested
|
2019-10-23 19:07:26 -04:00 |
|
felsabbagh3
|
b4d921f49a
|
set_top_level tcl
|
2019-10-23 11:56:32 -04:00 |
|
felsabbagh3
|
3cb5820ecd
|
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
|
2019-10-22 13:19:00 -04:00 |
|
felsabbagh3
|
f68942c92a
|
Added cache+shared memory search path
|
2019-10-22 13:18:49 -04:00 |
|
Shim
|
c43b3800d8
|
added report power and save ddc to synthesis script
|
2019-10-22 11:27:13 -04:00 |
|
felsabbagh3
|
9d8273afe4
|
Finished Cache Integration
|
2019-10-22 06:02:08 -04:00 |
|
felsabbagh3
|
b7af8c3f34
|
Integrated Shared Memory
|
2019-10-22 05:03:47 -04:00 |
|
felsabbagh3
|
1bfafca896
|
Cleanup before integration
|
2019-10-22 03:03:17 -04:00 |
|
Lingjun Zhu
|
eeb0a321a8
|
Finished synthesis with no optimization, cell count increasts to 100k
|
2019-10-21 17:53:51 -04:00 |
|
Lingjun Zhu
|
e2cd8102eb
|
Uncommented the necessary line about write_bit_mask on VX_gpr.v again, try synthesizing
|
2019-10-21 17:09:51 -04:00 |
|
felsabbagh3
|
fd876144f5
|
.tcl mod
|
2019-10-21 11:27:01 -04:00 |
|
felsabbagh3
|
bab1852a99
|
Added Split/Join - not tested
|
2019-10-21 03:03:15 -04:00 |
|
felsabbagh3
|
84f5ccb484
|
Added CSR TID/WID reads
|
2019-10-21 02:10:05 -04:00 |
|
felsabbagh3
|
f7b55427b4
|
Added ISA2 infrastructure with bugs
|
2019-10-18 05:21:32 -04:00 |
|
felsabbagh3
|
559c64cb36
|
Cleanup
|
2019-10-18 02:20:38 -04:00 |
|
felsabbagh3
|
505bbc20c8
|
Removed FWD
|
2019-10-18 02:01:39 -04:00 |
|
felsabbagh3
|
ccbb2acab5
|
LSU+EXU minor
|
2019-10-17 22:38:09 -04:00 |
|
felsabbagh3
|
6779d0fade
|
Instruction Multiplex LSU/EXU 1 cycle DONE
|
2019-10-17 22:29:21 -04:00 |
|
Lingjun Zhu
|
d164ebfbc6
|
Added log file of synthesis, too many registers are removed
|
2019-10-17 14:25:54 -04:00 |
|
Lingjun Zhu
|
a4d6ada16d
|
Fixed the issues of memory during synthesis
|
2019-10-17 14:18:52 -04:00 |
|
Shim
|
78e4067013
|
added log file
|
2019-10-17 14:00:22 -04:00 |
|
Shim
|
0bea82a2c3
|
added tcl file
|
2019-10-17 11:55:18 -04:00 |
|