felsabbagh3 8013708a5b Added fsyn for my synthesis

2019-10-27 22:16:57 -04:00

..

191017.log

added log file

2019-10-17 14:00:22 -04:00

cshrc.dc

Added fsyn for my synthesis

2019-10-27 22:16:57 -04:00

dc_noOpt.log

Finished synthesis with no optimization, cell count increasts to 100k

2019-10-21 17:53:51 -04:00

dc.log

Added log file of synthesis, too many registers are removed

2019-10-17 14:25:54 -04:00

fsyn.tcl

Added fsyn for my synthesis

2019-10-27 22:16:57 -04:00

Makefile

Added fsyn for my synthesis

2019-10-27 22:16:57 -04:00

NanGate_15nm_OCL.db

Added fsyn for my synthesis

2019-10-27 22:16:57 -04:00

syn.tcl

Added fsyn for my synthesis

2019-10-27 22:16:57 -04:00