Blaise Tine
43154cf738
minor updates
2023-11-16 23:41:59 -08:00
Hansung Kim
e2d3d93dea
Properly initialize DCR in wrapper code
2023-11-16 17:59:57 -08:00
Blaise Tine
d65cc61df5
minor update
2023-11-16 12:00:37 -08:00
Hansung Kim
963c2765d9
Move force-include of gpu_pkg to non-cache modules
2023-11-15 22:02:44 -08:00
Hansung Kim
448a253af3
Add Verilog wrapper module for VX_core
2023-11-15 20:09:53 -08:00
Hansung Kim
bbacf9a25e
Remove verilated vpi code, add missing includes for C++
...
Vortex rtlsim defines sim_trace_enabled... functions in the Verilated
C++ code for use in dpi_trace, which we don't need.
2023-11-15 20:06:58 -08:00
Hansung Kim
7e0b63a3b3
Change result type for dpi calls from wire -> reg
...
VCS requires the output of the dpi calls to be of a type that can come
at the LHS of a procedural assignment, i.e. reg type. Seems to be a
different requirement from Verilator.
2023-11-15 19:26:12 -08:00
Hansung Kim
d2d7ee61bb
Define SIMULATION for VCS in VX_platform.vh
2023-11-15 19:14:58 -08:00
Blaise Tine
547d916ae2
minor update
2023-11-15 13:00:06 -08:00
Blaise Tine
2c94e358b8
perf counter bug fix
2023-11-15 00:52:39 -08:00
Hansung Kim
512fc0da1c
Copy VX_platform macros for VCS from VERILATOR
2023-11-15 00:20:18 -08:00
Hansung Kim
20a9e6d102
Force include VX_gpu_pkg as compile order workaround
...
addResource() calls in Chisel BlackBox does not preserve order of the
files being included; the actual compile order for these files are
re-arranged to be in alphabetical order.
Therefore, while VX_gpu_pkg.sv has to be compiled before all the other
modules because it holds the top-level package definition, that order
cannot be ensured from Chisel. As a hacky workaround, simply `include
this file in some of the sv files whose name starts earlier than
VX_gpu_pkg in lexicographical order.
2023-11-14 23:00:43 -08:00
Blaise Tine
ecf546bc4a
minor update
2023-11-13 20:00:39 -08:00
Blaise Tine
b274b8cc21
minor updates
2023-11-13 00:23:15 -08:00
Blaise Tine
a08d3ebd42
minor update
2023-11-12 23:40:59 -08:00
Blaise Tine
62cdd8e993
minor update
2023-11-11 15:49:39 -08:00
Blaise Tine
c1e168fdbe
Vortex 2.0 changes:
...
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
minor update
minor update
minor update
minor update
minor update
minor update
cleanup
cleanup
cache bindings and memory perf refactory
minor update
minor update
hw unit tests fixes
minor update
minor update
minor update
minor update
minor update
minor udpate
minor update
minor update
minor update
minor update
minor update
minor update
minor update
minor updates
minor updates
minor update
minor update
minor update
minor update
minor update
minor update
minor updates
minor updates
minor updates
minor updates
minor update
minor update
2023-11-10 02:47:05 -08:00
Blaise Tine
6e93787e59
minor update
2023-11-06 00:16:24 -08:00
Blaise Tine
d13c5f2986
hw unit tests fixes
2023-11-05 18:51:31 -08:00
Blaise Tine
1fd5a95f5a
minor update
2023-11-03 18:04:05 -04:00
Blaise Tine
9f1f1ecaa3
minor update
2023-11-03 08:36:28 -04:00
Blaise Tine
c9e6518e05
cache bindings and memory perf refactory
2023-11-03 08:18:18 -04:00
Blaise Tine
69f9ae778d
cleanup
2023-11-03 08:12:03 -04:00
Blaise Tine
1c100c4cf5
minor update
2023-10-22 23:31:58 -07:00
Blaise Tine
8fe373891f
minor update
2023-10-21 17:55:29 -07:00
Blaise Tine
d47cccc157
Vortex 2.0 changes:
...
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
2023-10-19 20:51:22 -07:00
Blaise Tine
d69a64c32c
minor update
2023-05-16 04:59:01 -04:00
Santosh Srivatsan
b7e5a83ba3
Merged branch xlen-parameterization into staging
2022-02-05 13:47:42 -05:00
Santosh Srivatsan
836c777680
XLEN parameterization for simx
2022-02-03 15:19:31 -05:00
Blaise Tine
a06812f93f
minor updates
2022-02-01 22:51:33 -05:00
Blaise Tine
d48f1c1c5f
minor updates
2022-02-01 06:53:31 -05:00
Santosh Srivatsan
91c22a2592
Fixed some riscv-tests
2022-01-22 12:54:10 -05:00
Santosh Srivatsan
d762d401cd
Added 64-bit linker script
2022-01-11 17:22:16 -05:00
Santosh Srivatsan
f93303bac7
Minor update
2021-12-15 17:21:38 -05:00
Santosh Srivatsan
e82d5fe48f
Removed all comments labelled \'simx64\'
2021-12-13 19:52:13 -05:00
Santosh Srivatsan
5edb9098ce
Merge branch 'simx64'
2021-12-10 21:48:29 -05:00
Blaise Tine
d7737542e4
cache uuid support
2021-12-09 20:43:22 -05:00
Blaise Tine
38f166f090
texture unit hardware optimizations
2021-12-02 10:22:21 -08:00
Santosh Raghav Srivatsan
f0dc04ad04
Added tests to commit. 64 bit simx still not working
2021-12-01 02:44:14 -05:00
Blaise Tine
4477cbeed1
blackbox caching fix
2021-11-30 15:36:59 -05:00
Blaise Tine
41d7e6c63a
cummulative fixes, RTL uuid trace, texture unit fixes, simx timing fixes
2021-11-30 07:08:15 -05:00
Blaise Tine
b995843a5b
cocogfx fixes and refactoring
2021-11-25 13:58:09 -05:00
Blaise Tine
a671e1a05d
moving submodules into third_party folder
2021-11-24 18:10:00 -05:00
Blaise Tine
18762dffce
fixes: texture unit mem access sometimes going to smem, bilinear texture filtering; new: cache req_id,
2021-11-24 00:00:17 -05:00
Blaise Tine
9656779d48
minor update
2021-11-14 04:45:06 -05:00
Blaise Tine
bd70afa688
cache multi-porting fix - ensure per-bank uniform rw
2021-11-14 04:44:25 -05:00
Blaise Tine
fe862f64b1
dispatch refactoring
2021-10-19 15:16:00 -04:00
Blaise Tine
e248f744d5
Merge branch 'master' of https://github.com/vortexgpgpu/vortex
2021-10-19 03:07:13 -04:00
Blaise Tine
6edf38548f
text_unit merge fixes
2021-10-19 00:16:22 -04:00
Blaise Tine
0b23d8e935
minor update
2021-10-18 14:32:39 -04:00
