Commit Graph

57 Commits

Author SHA1 Message Date
Blaise Tine
7b8fe11e6a unused variables refactoring 2021-08-05 01:46:26 -07:00
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15e4d8b716 writeback refactoring 2021-07-26 11:25:30 -07:00
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a79253329c relaxing commit back-pressure in writeback stage 2021-03-15 14:39:55 -07:00
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062d02ddce Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2021-03-04 20:51:03 -08:00
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700f9eea19 moving MUL unit into ALU unit 2021-02-23 13:49:02 -08:00
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9f128085d5 scoreboard optimization - using writeback's end-of-packet status 2020-12-30 06:47:56 -08:00
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d44144f72f FPU float<->int conversion optimization 2020-12-29 15:37:45 -08:00
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b459192dec critical path optimization - fpga fmax @4c = ~212 mhz 2020-12-26 03:28:32 -08:00
Blaise Tine
4bbd7bf408 performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies, 2020-12-19 02:45:06 -08:00
Blaise Tine
13a5370254 register file refactoring 2020-12-05 01:40:50 -08:00
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fb60d0af87 decoupled load/store commits 2020-12-03 15:08:48 -08:00
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5758ef9ebf generic_register reset network optimization 2020-11-29 18:41:36 -08:00
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461be0880d fixed FPU-CSR data dependence 2020-11-25 09:05:38 -08:00
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34b650be94 fixed shared memory addressing critical path, fixed VX_fp_noncomp output bug 2020-11-17 00:27:24 -08:00
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2e0f51af80 fixed instr/cycle perf counter 2020-11-12 11:41:25 -08:00
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725322807e fixed DRAM response backpressure inside Cache 2020-11-10 05:24:57 -08:00
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32da50816f scope refactoring: adding modules definitions to VCD trace 2020-10-12 23:26:02 -04:00
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49b86c4b2a SCOPE update 2020-09-05 10:52:59 -07:00
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af84e01856 minor update 2020-08-31 06:17:49 -07:00
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0a0b28aac0 minor update - 206-214 mhz 2020-08-29 05:14:08 -07:00
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fde3f46798 ibuffer optimization 2020-08-26 04:44:36 -07:00
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f292e5003d quartus build fixes 2020-08-23 22:04:46 -07:00
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0b355f228e ibuffer addition 2020-08-22 00:22:04 -07:00
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6c12391338 pipeline refactoring - fmax >= 222 mhz 2020-08-14 21:50:14 -07:00
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65415d2bbc getting dogfood tests passing on Verilator! 2020-08-09 18:13:12 -04:00
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cd29362d10 fixed FPU handshake, optimized writeback's critical path 2020-08-07 10:11:54 -07:00
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ffd9515881 added altera fpu modules 2020-08-05 15:53:59 -07:00
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b8cd3b0b28 gpr pipeline optimization 2020-08-01 12:38:30 -04:00
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c9755a0c48 lkg build with pipeline + FPU fixes 2020-07-31 09:29:44 -04:00
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27e95530ef pipeline optimization 2020-07-30 03:06:01 -07:00
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60e05ae19a minor update 2020-07-28 22:45:43 -07:00
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97962a150b minor update 2020-07-28 14:28:54 -07:00
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c2dd0a8b39 modelsim fixes && pipeline optimization 2020-07-28 14:20:23 -07:00
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8976100025 floating point support fixes 2020-07-28 04:19:46 -04:00
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f01afcc5cd floating point support fixes + riscv-tests update 2020-07-28 02:19:11 -04:00
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e0a9089647 floating point support fixes 2020-07-27 16:01:56 -04:00
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ff12393998 floating point support fixes 2020-07-27 04:53:13 -04:00
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7c86b68977 pipeline refactoring: centralized issue buffer 2020-07-26 11:21:08 -04:00
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1f63f9da25 new fpu implementation 2020-07-24 00:00:37 -04:00
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75e3c31b56 fpu implementation (part1) 2020-07-23 03:18:09 -07:00
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e2100e9e87 pipeline refactoring 2020-07-20 09:38:54 -04:00
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577a5791dc pipeline refactoring 2020-07-20 08:04:04 -04:00
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25f66e6490 pipeline refactoring 2020-07-19 05:03:47 -04:00
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d6b0ef2b3c scope refactoring + snoop invalidate 2020-06-12 00:04:31 -07:00
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9e5885b820 adding dram writeenable support + scheduler bug fixes 2020-05-27 19:00:23 -04:00
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b7e892ee16 rtl refactoring 2020-05-05 10:46:48 -04:00
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a1dc90b951 rtl cache refactory 2020-04-30 17:12:18 -04:00
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d85c0af5d6 remove tab spaces 2020-04-21 03:19:47 -04:00
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ba4e736782 RTL code refactoring 2020-04-21 01:03:37 -04:00
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d79e36912f fix opae build 2020-04-20 12:51:42 -07:00