Blaise Tine
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7529f72c5d
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fixed OPAE crash, added custom bram module to controll rw collision, dogfood testcase argurment, optimzed buffered fifo, quartus build optimization flags
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2020-10-20 05:32:55 -07:00 |
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Blaise Tine
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32da50816f
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scope refactoring: adding modules definitions to VCD trace
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2020-10-12 23:26:02 -04:00 |
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Blaise Tine
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4e1007e5b2
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scope refactoring
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2020-10-03 18:53:21 -04:00 |
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Blaise Tine
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f6f95e0c46
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mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL
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2020-09-19 14:45:42 -04:00 |
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Blaise Tine
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31ffbe0d6a
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clean up 'stage_1_cycles' from cache
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2020-09-01 03:39:03 -07:00 |
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Blaise Tine
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af84e01856
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minor update
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2020-08-31 06:17:49 -07:00 |
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Blaise Tine
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0b355f228e
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ibuffer addition
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2020-08-22 00:22:04 -07:00 |
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Blaise Tine
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6c12391338
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pipeline refactoring - fmax >= 222 mhz
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2020-08-14 21:50:14 -07:00 |
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Blaise Tine
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65415d2bbc
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getting dogfood tests passing on Verilator!
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2020-08-09 18:13:12 -04:00 |
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Blaise Tine
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c9755a0c48
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lkg build with pipeline + FPU fixes
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2020-07-31 09:29:44 -04:00 |
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Blaise Tine
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7c86b68977
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pipeline refactoring: centralized issue buffer
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2020-07-26 11:21:08 -04:00 |
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Blaise Tine
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1f63f9da25
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new fpu implementation
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2020-07-24 00:00:37 -04:00 |
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Blaise Tine
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25f66e6490
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pipeline refactoring
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2020-07-19 05:03:47 -04:00 |
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felsabbagh3
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14e4fd95b7
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Don't allow snrq scheduling if there's a valid reqq entry (Event if it can't be scheduled)
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2020-06-29 00:03:36 -07:00 |
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felsabbagh3
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567376971e
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Added dram_fill_req_fast which is used to stall bank pipeline
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2020-06-28 15:22:36 -07:00 |
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felsabbagh3
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c95d3cb22b
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Added cache critical path optimizations
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2020-06-27 16:12:22 -07:00 |
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Blaise Tine
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baf7d3bb92
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minor update
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2020-06-27 17:46:45 -04:00 |
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Blaise Tine
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bc0c65dce7
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2020-06-27 13:56:44 -07:00 |
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Blaise Tine
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8302641510
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fpga fixes
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2020-06-27 14:03:20 -07:00 |
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Blaise Tine
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8a306de02d
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runtime static library
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2020-06-27 14:13:13 -04:00 |
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Blaise Tine
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d3440de403
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round robin arbiter + auto buffered queue + fixed dcache arbiter
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2020-06-20 17:56:04 -04:00 |
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Blaise Tine
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68d9fc9a75
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driver basic test and demo test refactoring
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2020-06-19 09:12:07 -07:00 |
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Blaise Tine
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d6b0ef2b3c
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scope refactoring + snoop invalidate
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2020-06-12 00:04:31 -07:00 |
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Blaise Tine
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171d46b501
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fix l2 cache issues
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2020-06-04 18:34:14 -04:00 |
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Blaise Tine
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ea890b457d
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fixed msrq regression
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2020-06-03 17:22:24 -04:00 |
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Blaise Tine
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9b186dcc6e
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fixed L2 cache
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2020-06-02 05:32:50 -07:00 |
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Blaise Tine
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e01c411b20
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opae rtl fixes
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2020-06-01 23:06:13 -07:00 |
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Blaise Tine
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33b273b204
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-05-28 18:34:25 -04:00 |
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Blaise Tine
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b930a822ad
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minor updates
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2020-05-28 18:34:03 -04:00 |
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Blaise Tine
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9e5885b820
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adding dram writeenable support + scheduler bug fixes
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2020-05-27 19:00:23 -04:00 |
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Blaise Tine
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61231cd2af
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OPAE rtl fixes
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2020-05-24 02:42:56 -07:00 |
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Blaise Tine
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a9f896b4f3
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fixed snoop forwarding bug and single bank support
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2020-05-24 04:29:43 -04:00 |
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felsabbagh3
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a1e9b512b0
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Added mrvq_recover_ready_state_st2 to optimize fills sent
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2020-05-23 21:47:51 -07:00 |
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felsabbagh3
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0cd9bd689e
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Added schedule_ptr to mrvq for speculative pops
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2020-05-23 21:36:57 -07:00 |
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Blaise Tine
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6882d88a62
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removed fill_invalidator (not needed anymore)
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2020-05-23 19:24:52 -04:00 |
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Blaise Tine
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f3b21aab8f
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remove unsued cache parameter LLVQ_SIZE
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2020-05-23 00:33:51 -04:00 |
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Blaise Tine
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b02fc14da6
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fill invalifator fix + refactoring
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2020-05-21 20:38:55 -07:00 |
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Blaise Tine
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cf22ef2bf3
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minor update
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2020-05-21 13:42:08 -04:00 |
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Blaise Tine
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cefd0d85af
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rtl refactoring
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2020-05-20 16:59:14 -04:00 |
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Blaise Tine
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b5569dd525
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OPAE rtl fixes
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2020-05-20 12:08:10 -07:00 |
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Blaise Tine
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e269909db9
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opae rtl fixes
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2020-05-19 13:47:47 -07:00 |
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Blaise Tine
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0c88da2bfb
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opae rtl fixes
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2020-05-18 20:19:02 -07:00 |
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Blaise Tine
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11ace25f27
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opae rtl fixes
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2020-05-17 20:29:42 -07:00 |
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felsabbagh3
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26f9fc96c3
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Corner case where the pipeline is stalled, makes mrvq entereis valid, but when unstalled mrvq_init isn't set up correctly
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2020-05-16 21:20:57 -07:00 |
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felsabbagh3
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101de6b138
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mrvq update ready + init ready as 1 in same cycle causing incorrect ready state
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2020-05-16 18:52:30 -07:00 |
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felsabbagh3
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e2741f9cdb
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Force miss_add init ready to 1 when core req matches with mrvq entry, regardless of hit/miss
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2020-05-16 16:26:26 -07:00 |
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Blaise Tine
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d6c87dbb0a
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added debug print states or rtl
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2020-05-16 14:19:17 -04:00 |
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Blaise Tine
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d623ef4029
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snooping response handling fix
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2020-05-14 23:05:46 -04:00 |
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Blaise Tine
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bcb9514799
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snooping response handling fix
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2020-05-14 11:01:41 -04:00 |
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felsabbagh3
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ff140b6811
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Added an initial ready state to an mrvq entry that might be set to 1
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2020-05-12 21:47:51 -07:00 |
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