Blaise Tine
c1e168fdbe
Vortex 2.0 changes:
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+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
minor update
minor update
minor update
minor update
minor update
minor update
cleanup
cleanup
cache bindings and memory perf refactory
minor update
minor update
hw unit tests fixes
minor update
minor update
minor update
minor update
minor update
minor udpate
minor update
minor update
minor update
minor update
minor update
minor update
minor update
minor updates
minor updates
minor update
minor update
minor update
minor update
minor update
minor update
minor updates
minor updates
minor updates
minor updates
minor update
minor update
2023-11-10 02:47:05 -08:00
Blaise Tine
d7737542e4
cache uuid support
2021-12-09 20:43:22 -05:00
Blaise Tine
41d7e6c63a
cummulative fixes, RTL uuid trace, texture unit fixes, simx timing fixes
2021-11-30 07:08:15 -05:00
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fe862f64b1
dispatch refactoring
2021-10-19 15:16:00 -04:00
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e380ded5e1
Merge branch 'master' into graphics
2021-10-15 19:32:11 -07:00
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1cd833d2c4
minor fixes
2021-10-11 19:02:13 -07:00
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29aba92bf1
minor update
2021-09-30 06:14:05 -07:00
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a801a16062
instruction decode refactoring fixing naming collision
2021-08-29 20:07:34 -07:00
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4336dcb2a8
minor scope analyzer fix
2021-08-13 19:23:57 -07:00
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cc259f60f6
minor update
2021-08-11 15:39:21 -07:00
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4e4aa33a50
minor update
2021-08-08 03:09:28 -07:00
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0debdd3fe7
minor update
2021-08-08 02:59:30 -07:00
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b1eef0fb7c
warp scheduler optimization
2021-08-07 23:45:01 -07:00
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7b921387bc
Merge branch 'master' into graphics
2021-08-02 23:57:53 -07:00
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3b7da61245
minor update
2021-07-31 03:30:35 -07:00
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ee46bc8a48
minor update
2021-07-31 03:02:25 -07:00
Blaise Tine
94ad34768b
Merge branch 'graphics' of https://github.com/vortexgpgpu/vortex-dev into graphics
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Conflicts:
hw/rtl/VX_core.v
hw/rtl/VX_csr_data.v
hw/rtl/VX_csr_unit.v
hw/rtl/VX_decode.v
hw/rtl/VX_define.vh
hw/rtl/VX_execute.v
hw/rtl/VX_gpu_unit.v
hw/rtl/VX_instr_demux.v
hw/rtl/VX_lsu_unit.v
hw/rtl/VX_mem_unit.v
hw/rtl/VX_pipeline.v
hw/rtl/VX_platform.vh
hw/rtl/VX_smem_arb.v
hw/rtl/VX_writeback.v
hw/rtl/cache/VX_bank.v
hw/rtl/interfaces/VX_cache_mem_req_if.v
hw/rtl/interfaces/VX_cache_mem_rsp_if.v
hw/rtl/interfaces/VX_dcache_core_rsp_if.v
hw/rtl/interfaces/VX_dcache_req_if.v
hw/rtl/interfaces/VX_icache_core_rsp_if.v
hw/rtl/tex_unit/VX_tex_memory.v
hw/rtl/tex_unit/VX_tex_unit.v
hw/simulate/Makefile
hw/syn/quartus/pipeline/Makefile
hw/unit_tests/tex_unit/tex_sampler/main.cpp
hw/unit_tests/tex_unit/tex_sampler/vl_simulator.h
runtime/include/vx_intrinsics.h
2021-07-30 21:12:55 -07:00
Blaise Tine
4ffbcb336f
minor update
2021-07-22 14:20:02 -07:00
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7e0dc81cee
minor update
2021-06-23 04:19:13 -07:00
Blaise Tine
41069ba188
non-cacheable memory address fixes
2021-06-06 20:54:36 -07:00
Blaise Tine
3071fb7a29
adding support for non-cacheable memory addressing
2021-06-06 13:35:55 -07:00
Blaise Tine
30a39afbf6
master merge fixes
2021-05-27 16:50:03 -07:00
Blaise Tine
762c5da237
minor update
2021-05-27 15:23:58 -07:00
Blaise Tine
d42171d2ed
Merge branch 'master' into graphics
2021-05-26 23:33:06 -07:00
Blaise Tine
8f451aa74c
minor update
2021-05-04 08:01:49 -07:00
Blaise Tine
8410c49f53
code refactoring: DRAM => MEM renaming
2021-04-26 00:58:48 -07:00
Blaise Tine
4cb98a25a7
enabling 128-bit dram bus
2021-04-24 00:31:27 -04:00
Blaise Tine
676a13f30d
tex refactoring and bug fixes
2021-03-16 09:25:57 -04:00
Blaise Tine
b023496ecb
minor update
2021-03-01 03:00:58 -08:00
Blaise Tine
7560202f8b
cache bank refactoring - removing unecessary core response fifo & restoring single port data access
2021-02-21 21:47:46 -08:00
Blaise Tine
a046bd7a73
cache pipeline optimization
2021-01-17 17:19:52 -08:00
Blaise Tine
d4e7b28be8
cache refactoring
2021-01-17 00:18:56 -08:00
Blaise Tine
5b80484123
minor updates
2021-01-16 14:16:10 -08:00
Blaise Tine
fe64c47f60
ccip write fix
2021-01-14 22:49:06 -08:00
Blaise Tine
464c4f4bd8
minor updates
2021-01-12 20:16:59 -08:00
Blaise Tine
f18ac24675
afu reset fix
2021-01-12 17:13:47 -08:00
Blaise Tine
4d55118545
cache pipeline optimization - moved tag access to stage0
2021-01-03 23:10:41 -05:00
Blaise Tine
abe32ed553
cache optimization - moved read requests to stage1 and eliminating stage3
2020-12-31 07:40:58 -08:00
Blaise Tine
9f128085d5
scoreboard optimization - using writeback's end-of-packet status
2020-12-30 06:47:56 -08:00
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3fdc49971c
minor update
2020-12-24 09:22:44 -08:00
Blaise Tine
4bbd7bf408
performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
2020-12-19 02:45:06 -08:00
Blaise Tine
13a5370254
register file refactoring
2020-12-05 01:40:50 -08:00
Blaise Tine
def6a35693
shared memory optimization
2020-11-29 15:04:31 -08:00
Blaise Tine
b85391389b
rename MSRQ to MSHR
2020-11-28 17:32:00 -05:00
Blaise Tine
1795980a52
L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
2020-11-21 09:47:56 -08:00
Blaise Tine
af2bb3b789
cache fixes and opyimization - fmax moved from 162 mhz to 220 mhz!!!
2020-11-05 03:49:50 -08:00
Blaise Tine
4c6a74fa87
cache refactoring - phase 3 - added dedicated pipeline stage for tag access
2020-11-04 03:21:30 -08:00
Blaise Tine
3fe31fc337
fixed afu to cpu mempcy hang
2020-10-28 14:19:13 -07:00
Blaise Tine
9a9f7955f0
basic test timing + scope tracing ccip
2020-10-27 17:04:04 -04:00
Blaise Tine
58b8e82908
scope fixes ...
2020-10-13 17:09:22 -04:00
