Commit Graph

48 Commits

Author SHA1 Message Date
Blaise Tine
5d58bf3d11 fixed l3cache hang using memory arbiter in afu 2020-11-15 06:36:32 -08:00
Blaise Tine
725322807e fixed DRAM response backpressure inside Cache 2020-11-10 05:24:57 -08:00
Blaise Tine
203a184008 fixed bank_core_req_abr critical path 2020-11-08 18:25:32 -08:00
Blaise Tine
af2bb3b789 cache fixes and opyimization - fmax moved from 162 mhz to 220 mhz!!! 2020-11-05 03:49:50 -08:00
Blaise Tine
4c6a74fa87 cache refactoring - phase 3 - added dedicated pipeline stage for tag access 2020-11-04 03:21:30 -08:00
Blaise Tine
cd8ce20bd6 minor improvement 2020-11-03 17:08:26 -08:00
Blaise Tine
323d2a3b3e minor fix 2020-11-03 15:34:35 -08:00
Blaise Tine
ba81d76e02 cache refactoring - phase 2 2020-11-03 04:51:40 -08:00
Blaise Tine
5be1d85648 cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count 2020-11-02 01:50:12 -08:00
Blaise Tine
43ae82e788 vlsim fix, verilator fst trace, use ram optimization 2020-10-25 16:40:50 -07:00
Blaise Tine
7529f72c5d fixed OPAE crash, added custom bram module to controll rw collision, dogfood testcase argurment, optimzed buffered fifo, quartus build optimization flags 2020-10-20 05:32:55 -07:00
Blaise Tine
32da50816f scope refactoring: adding modules definitions to VCD trace 2020-10-12 23:26:02 -04:00
Blaise Tine
4e1007e5b2 scope refactoring 2020-10-03 18:53:21 -04:00
Blaise Tine
0b355f228e ibuffer addition 2020-08-22 00:22:04 -07:00
Blaise Tine
6c12391338 pipeline refactoring - fmax >= 222 mhz 2020-08-14 21:50:14 -07:00
Blaise Tine
7c86b68977 pipeline refactoring: centralized issue buffer 2020-07-26 11:21:08 -04:00
Blaise Tine
dc7efbcfb4 pipeline refactoring 2020-07-21 05:22:47 -04:00
Blaise Tine
bdfacf709c yosys synthesis refactoring 2020-07-10 18:56:41 -04:00
Blaise Tine
8302641510 fpga fixes 2020-06-27 14:03:20 -07:00
Blaise Tine
0a01385a2c few updates 2020-06-23 09:28:24 -07:00
Blaise Tine
d3440de403 round robin arbiter + auto buffered queue + fixed dcache arbiter 2020-06-20 17:56:04 -04:00
Blaise Tine
68d9fc9a75 driver basic test and demo test refactoring 2020-06-19 09:12:07 -07:00
Blaise Tine
d6b0ef2b3c scope refactoring + snoop invalidate 2020-06-12 00:04:31 -07:00
Blaise Tine
171d46b501 fix l2 cache issues 2020-06-04 18:34:14 -04:00
Blaise Tine
ea890b457d fixed msrq regression 2020-06-03 17:22:24 -04:00
Blaise Tine
04fc34b848 minor update 2020-06-03 03:05:45 -07:00
Blaise Tine
9b186dcc6e fixed L2 cache 2020-06-02 05:32:50 -07:00
Blaise Tine
9e5885b820 adding dram writeenable support + scheduler bug fixes 2020-05-27 19:00:23 -04:00
Blaise Tine
a9f896b4f3 fixed snoop forwarding bug and single bank support 2020-05-24 04:29:43 -04:00
felsabbagh3
0cd9bd689e Added schedule_ptr to mrvq for speculative pops 2020-05-23 21:36:57 -07:00
Blaise Tine
72d54c749c fixed cache msrq reset logic 2020-05-20 18:11:31 -04:00
Blaise Tine
cefd0d85af rtl refactoring 2020-05-20 16:59:14 -04:00
Blaise Tine
b5569dd525 OPAE rtl fixes 2020-05-20 12:08:10 -07:00
Blaise Tine
11ace25f27 opae rtl fixes 2020-05-17 20:29:42 -07:00
felsabbagh3
101de6b138 mrvq update ready + init ready as 1 in same cycle causing incorrect ready state 2020-05-16 18:52:30 -07:00
Blaise Tine
bcb9514799 snooping response handling fix 2020-05-14 11:01:41 -04:00
felsabbagh3
ff140b6811 Added an initial ready state to an mrvq entry that might be set to 1 2020-05-12 21:47:51 -07:00
felsabbagh3
b08b80156d Added pending request check. This applies when 1) mrvq entery is valid/ready but not head, then a core request hits 2) snoop when pending write. A pending miss request is either a valid entry in mrvq OR a miss entery in st2 2020-05-12 21:25:13 -07:00
Blaise Tine
b0b38f6c24 snooping response handling fix 2020-05-12 18:52:24 -04:00
Blaise Tine
c49f01b769 snooping response handling 2020-05-11 22:55:44 -04:00
Blaise Tine
cc84e0691c multicore fix 2020-05-10 08:30:04 -04:00
Blaise Tine
13dfd5c8c7 rtl multicore fix 2020-05-07 02:20:12 -04:00
Blaise Tine
330bbc4f56 rtl gpr multicore fix 2020-05-06 09:05:10 -04:00
Blaise Tine
b7e892ee16 rtl refactoring 2020-05-05 10:46:48 -04:00
Blaise Tine
f142afac80 rtl refactoring 2020-05-04 20:12:05 -04:00
Blaise Tine
a1dc90b951 rtl cache refactory 2020-04-30 17:12:18 -04:00
Blaise Tine
d85c0af5d6 remove tab spaces 2020-04-21 03:19:47 -04:00
Blaise Tine
e8a4923eb4 RTL code refactoring 2020-04-20 12:09:30 -04:00