207 lines
8.8 KiB
Verilog
207 lines
8.8 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_cache_miss_resrv #(
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parameter CACHE_ID = 0,
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parameter BANK_ID = 0,
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parameter CORE_TAG_ID_BITS = 0,
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// Size of line inside a bank in bytes
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parameter BANK_LINE_SIZE = 0,
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// Number of banks {1, 2, 4, 8,...}
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parameter NUM_BANKS = 0,
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// Size of a word in bytes
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parameter WORD_SIZE = 0,
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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parameter NUM_REQUESTS = 0,
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// Miss Reserv Queue Knob
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parameter MRVQ_SIZE = 0,
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// core request tag size
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parameter CORE_TAG_WIDTH = 0,
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// Snooping request tag width
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parameter SNP_REQ_TAG_WIDTH = 0
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) (
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input wire clk,
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input wire reset,
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`ifdef DBG_CORE_REQ_INFO
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`IGNORE_WARNINGS_BEGIN
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input wire[31:0] debug_pc_st0,
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input wire[`NR_BITS-1:0] debug_rd_st0,
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input wire[`NW_BITS-1:0] debug_wid_st0,
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input wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st0,
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input wire[31:0] debug_pc_st2,
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input wire[`NR_BITS-1:0] debug_rd_st2,
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input wire[`NW_BITS-1:0] debug_wid_st2,
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input wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_tagid_st2,
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`IGNORE_WARNINGS_END
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`endif
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// enqueue
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input wire miss_add,
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input wire[`LINE_ADDR_WIDTH-1:0] miss_add_addr,
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input wire[`UP(`WORD_SELECT_WIDTH)-1:0] miss_add_wsel,
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input wire[`WORD_WIDTH-1:0] miss_add_data,
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input wire[`REQS_BITS-1:0] miss_add_tid,
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input wire[`REQ_TAG_WIDTH-1:0] miss_add_tag,
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input wire miss_add_rw,
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input wire[WORD_SIZE-1:0] miss_add_byteen,
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input wire miss_add_is_snp,
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input wire miss_add_snp_invalidate,
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input wire is_msrq_st2,
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input wire init_ready_state_st2,
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output wire miss_resrv_full,
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output wire miss_resrv_almfull,
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// fill
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input wire update_ready_st0,
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input wire[`LINE_ADDR_WIDTH-1:0] fill_addr_st0,
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output wire pending_hazard_st0,
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// dequeue
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input wire miss_resrv_schedule_st0,
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output wire miss_resrv_valid_st0,
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output wire[`LINE_ADDR_WIDTH-1:0] miss_resrv_addr_st0,
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output wire[`UP(`WORD_SELECT_WIDTH)-1:0] miss_resrv_wsel_st0,
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output wire[`WORD_WIDTH-1:0] miss_resrv_data_st0,
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output wire[`REQS_BITS-1:0] miss_resrv_tid_st0,
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output wire[`REQ_TAG_WIDTH-1:0] miss_resrv_tag_st0,
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output wire miss_resrv_rw_st0,
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output wire[WORD_SIZE-1:0] miss_resrv_byteen_st0,
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output wire miss_resrv_is_snp_st0,
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output wire miss_resrv_snp_invalidate_st0,
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input wire miss_resrv_pop_st2
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);
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localparam FULL_DISTANCE = 2; // need 2 cycles window to prevent pipeline lock
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wire [`MRVQ_METADATA_WIDTH-1:0] metadata_table;
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`NO_RW_RAM_CHECK reg [`LINE_ADDR_WIDTH-1:0] addr_table [MRVQ_SIZE-1:0];
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reg [MRVQ_SIZE-1:0] valid_table;
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reg [MRVQ_SIZE-1:0] ready_table;
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reg [`LOG2UP(MRVQ_SIZE)-1:0] schedule_ptr, restore_ptr;
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reg [`LOG2UP(MRVQ_SIZE)-1:0] head_ptr;
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reg [`LOG2UP(MRVQ_SIZE)-1:0] tail_ptr;
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reg [`LOG2UP(MRVQ_SIZE+1)-1:0] size;
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`STATIC_ASSERT(MRVQ_SIZE > FULL_DISTANCE, ("invalid size"))
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assign miss_resrv_full = (size == $bits(size)'(MRVQ_SIZE));
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assign miss_resrv_almfull = (size >= $bits(size)'(MRVQ_SIZE-FULL_DISTANCE));
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wire [MRVQ_SIZE-1:0] valid_address_match;
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for (genvar i = 0; i < MRVQ_SIZE; i++) begin
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assign valid_address_match[i] = valid_table[i] && (addr_table[i] == fill_addr_st0);
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end
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assign pending_hazard_st0 = (| valid_address_match);
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wire dequeue_ready = valid_table[schedule_ptr] && ready_table[schedule_ptr];
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assign miss_resrv_valid_st0 = dequeue_ready;
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assign miss_resrv_addr_st0 = addr_table[schedule_ptr];
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assign {miss_resrv_data_st0,
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miss_resrv_tid_st0,
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miss_resrv_tag_st0,
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miss_resrv_rw_st0,
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miss_resrv_byteen_st0,
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miss_resrv_wsel_st0,
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miss_resrv_is_snp_st0,
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miss_resrv_snp_invalidate_st0} = metadata_table;
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wire msrq_push = miss_add && !is_msrq_st2;
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wire [`LOG2UP(MRVQ_SIZE)-1:0] head_ptr_n = head_ptr + $bits(head_ptr)'(1);
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always @(posedge clk) begin
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if (reset) begin
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valid_table <= 0;
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ready_table <= 0;
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schedule_ptr <= 0;
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restore_ptr <= 0;
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head_ptr <= 0;
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tail_ptr <= 0;
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size <= 0;
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end else begin
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if (update_ready_st0) begin
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ready_table <= ready_table | valid_address_match;
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end
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if (miss_add) begin
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assert(!miss_resrv_full);
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if (is_msrq_st2) begin
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// returning missed msrq entry, restore schedule
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valid_table[restore_ptr] <= 1;
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ready_table[restore_ptr] <= init_ready_state_st2;
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restore_ptr <= restore_ptr + $bits(restore_ptr)'(1);
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schedule_ptr <= head_ptr;
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end else begin
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valid_table[tail_ptr] <= 1;
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ready_table[tail_ptr] <= init_ready_state_st2;
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addr_table[tail_ptr] <= miss_add_addr;
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tail_ptr <= tail_ptr + $bits(tail_ptr)'(1);
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size <= size + $bits(size)'(1);
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end
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end else if (miss_resrv_pop_st2) begin
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head_ptr <= head_ptr_n;
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restore_ptr <= head_ptr_n;
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valid_table[head_ptr] <= 0;
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size <= size - $bits(size)'(1);
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end
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if (miss_resrv_schedule_st0) begin
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assert(miss_resrv_valid_st0);
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valid_table[schedule_ptr] <= 0;
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schedule_ptr <= schedule_ptr + $bits(schedule_ptr)'(1);
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end
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end
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end
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VX_dp_ram #(
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.DATAW(`MRVQ_METADATA_WIDTH),
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.SIZE(MRVQ_SIZE),
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.BYTEENW(1),
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.BUFFERED(0),
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.RWCHECK(1)
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) metadata (
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.clk(clk),
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.waddr(tail_ptr),
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.raddr(schedule_ptr),
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.wren(msrq_push),
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.rden(1'b1),
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.din({miss_add_data, miss_add_tid, miss_add_tag, miss_add_rw, miss_add_byteen, miss_add_wsel, miss_add_is_snp, miss_add_snp_invalidate}),
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.dout(metadata_table)
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);
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`ifdef DBG_PRINT_CACHE_MSRQ
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always @(posedge clk) begin
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if (miss_add || miss_resrv_schedule_st0 || miss_resrv_pop_st2) begin
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if (miss_add)
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if (is_msrq_st2)
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$write("%t: cache%0d:%0d msrq-restore addr%0d=%0h ready=%b", $time, CACHE_ID, BANK_ID, restore_ptr, `LINE_TO_BYTE_ADDR(miss_add_addr, BANK_ID), init_ready_state_st2);
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else
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$write("%t: cache%0d:%0d msrq-push addr%0d=%0h ready=%b wid=%0d PC=%0h", $time, CACHE_ID, BANK_ID, tail_ptr, `LINE_TO_BYTE_ADDR(miss_add_addr, BANK_ID), init_ready_state_st2, debug_wid_st2, debug_pc_st2);
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else if (miss_resrv_schedule_st0)
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$write("%t: cache%0d:%0d msrq-schedule wid=%0d PC=%0h", $time, CACHE_ID, BANK_ID, debug_wid_st0, debug_pc_st0);
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else if (miss_resrv_pop_st2)
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$write("%t: cache%0d:%0d msrq-pop addr%0d wid=%0d PC=%0h", $time, CACHE_ID, BANK_ID, head_ptr, debug_wid_st2, debug_pc_st2);
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for (integer j = 0; j < MRVQ_SIZE; j++) begin
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if (valid_table[j]) begin
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$write(" ");
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if (schedule_ptr == $bits(schedule_ptr)'(j)) $write("*");
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if (~ready_table[j]) $write("!");
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$write("addr%0d=%0h", j, `LINE_TO_BYTE_ADDR(addr_table[j], BANK_ID));
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end
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else if (schedule_ptr == $bits(schedule_ptr)'(j)) begin
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$write(" *");
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if (~ready_table[j]) $write("!");
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$write("[addr%0d=%0h]", j, `LINE_TO_BYTE_ADDR(addr_table[j], BANK_ID));
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end
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end
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$write("\n");
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end
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end
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`endif
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endmodule |