wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
2,363 Commits 7 Branches 0 Tags
4aad161739773581a1df4037478e23a186d23cf2
Commit Graph
219 Commits
Author SHA1 Message Date
Richard Yan b70df8cbc9 proper srams 2024-05-07 13:52:07 -07:00
Richard Yan 85213d2876 synthesizable design 2024-04-17 18:05:51 -07:00
Richard Yan 8de5470da4 round robin warp scheduling 2024-04-16 23:03:00 -07:00
Hansung Kim b63333a4ec Merge remote-tracking branch 'upstream/master' into vortex2 2024-03-07 14:45:48 -08:00
Hansung Kim e7b0a149c7 Print TAG_ONLY_WIDTH of req_tag in trace 
... for use in trace parser.  Full req_tag includes debug information
that complicates matching request to a corresponding request by tag.
 2024-03-04 21:10:59 -08:00
Blaise Tine be0db6e1a5 minor update 2024-02-04 20:32:05 -08:00
Blaise Tine 6f7a389a1f arbiters unlock refactoring 2024-02-04 20:16:18 -08:00
Hansung Kim 48558982f7 Merge remote-tracking branch 'upstream/master' into vortex2 2024-02-01 23:35:58 -08:00
Blaise Tine f9cd8be19e minor update 2024-01-31 13:35:43 -08:00
Blaise Tine e2d1387df8 elastic buffers classification 2024-01-31 00:39:37 -08:00
Blaise Tine e04e026a14 profiling update 
minor updates
 2023-12-18 04:43:44 -08:00
Blaise Tine c6845a4c8d profiling timing optimization 
minor update

minor update

minor update
 2023-12-18 04:43:10 -08:00
Blaise Tine 6c7ac35054 profiling optimizations 
minor updates
 2023-12-18 04:43:00 -08:00
Blaise Tine 24973ffca0 scoreboard optimization & profiling 2023-11-27 05:53:36 -08:00
Blaise Tine ebec982434 minor update 2023-11-27 02:04:53 -08:00
Hansung Kim 90e21e8e58 [CHANGE] Work around uninitialized signal issue with === operator 
It seems many of the initial arch/uarch states, including the GPR, are
uninitialized in the VCS simulation, which results in functional errors caused
by propagated X's.  In this particular case it resulted in a dcache request not
being fired due to the rs1 data for an lw instruction having values as X,
causing the smem_unit to not arbitrate the request correctly.

A workaround of this issue is to stop the X propagation by using the
===-operation instead of == in the GPR unit, which had been the main source of X
propagation into the raddr port of the GPR.

Also, we run the simulation with GSR_RESET set to 1 so that the contents of the
GPR are initialized at the beginning of the simulation (however, this alone does
not prevent reading in X's, hence this fix.)

FIXME: This is a slight deviation from the upstream code; ideally, we want to do
clean & full initialization of microarchitectural states.
 2023-11-17 17:20:54 -08:00
Blaise Tine d13c5f2986 hw unit tests fixes 2023-11-05 18:51:31 -08:00
Blaise Tine d47cccc157 Vortex 2.0 changes: 
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
 2023-10-19 20:51:22 -07:00
Blaise Tine d48f1c1c5f minor updates 2022-02-01 06:53:31 -05:00
Blaise Tine 41d7e6c63a cummulative fixes, RTL uuid trace, texture unit fixes, simx timing fixes 2021-11-30 07:08:15 -05:00
Blaise Tine bf72800676 debug tracing refactoring 2021-10-17 13:42:16 -07:00
Blaise Tine 8e82ee00a0 minor update 2021-09-29 09:32:21 -07:00
Blaise Tine 04249c3ee9 code refactoring for Vivado compatibility 2021-09-29 04:48:53 -04:00
Blaise Tine a45261b530 code refactoring for Vivado compatibility 2021-09-29 03:24:17 -04:00
Blaise Tine 132260d84c minor update 2021-09-27 09:23:58 -04:00
Blaise Tine 9f34b2944c code refactoring for Vivado, sv2v, and yosys compatibility 2021-09-27 08:55:10 -04:00
Blaise Tine 9b04f3d9d6 Updated README and synthesis scripts 2021-09-22 07:50:47 -07:00
Blaise Tine feca2db24e critical path optimizations 2021-09-15 04:50:45 -07:00
Blaise Tine 83d80c061f Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2021-09-14 05:11:28 -04:00
Blaise Tine 3d7baf1640 block ram read enable fix 2021-09-14 01:45:01 -07:00
Blaise Tine 6652e2f0e9 minor update 2021-09-11 18:16:08 -07:00
Blaise Tine 6f09fb8ba5 Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2021-09-11 18:26:08 -04:00
Blaise Tine 95287980af minor update 2021-09-11 15:14:17 -07:00
Blaise Tine 0dfdf6cd4d Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2021-09-10 06:03:32 -04:00
Blaise Tine 5192846c72 minor updates 2021-09-10 02:57:05 -07:00
Blaise Tine 18172fa611 AXI memory bus support 2021-09-10 01:36:01 -07:00
Blaise Tine ca46b0a0be OUTPUT_REG => OUT_REG renaming 2021-09-09 03:05:38 -07:00
Blaise Tine a46c32ed4b Adding Vortex Yosys build support 2021-09-08 23:04:33 -04:00
Blaise Tine c06efbf480 minor update 2021-09-07 23:47:41 -07:00
Blaise Tine 0d91f8771e Workaround fix for Verilator bug with array indexing 2021-09-07 23:28:54 -07:00
Blaise Tine d42baf34ff minor update 2021-09-06 23:44:31 -07:00
Blaise Tine af1cecae07 stream arbiter update 2021-09-06 23:38:20 -07:00
Blaise Tine b52ace5142 area optimization bundle 2021-09-05 23:35:44 -07:00
Blaise Tine fe5112b6c1 minor updates 2021-09-05 23:05:21 -07:00
Blaise Tine 377466ed1c fpu area optimization 2021-09-05 21:01:52 -07:00
Blaise Tine f3ba27b138 GPRs optimization - disabling BRAM's read-during-write bypass block. 2021-08-28 15:34:36 -07:00
Blaise Tine 28eb3cfdb2 minor update 2021-08-26 14:49:57 -07:00
Blaise Tine 74a45e2772 stream arbiter optimization (using indexing instead of onehot mux) 2021-08-26 09:52:13 -07:00
Blaise Tine d91d56d126 block ram refactoring (multi-porting supporting and simulation support) 2021-08-26 08:19:44 -07:00
Blaise Tine e494860f38 using lzc instead of priority_encoder 2021-08-26 07:29:47 -07:00