Blaise Tine 9f34b2944c code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00

..

VX_axi_adapter.v

code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00

VX_bits_insert.v

minor update

2021-07-30 16:01:22 -07:00

VX_bits_remove.v

minor update

2021-07-30 16:01:22 -07:00

VX_bypass_buffer.v

code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00

VX_divider.v

Disabling tracing on library

2021-08-12 01:55:52 -07:00

VX_dp_ram.v

code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00

VX_elastic_buffer.v

block ram read enable fix

2021-09-14 01:45:01 -07:00

VX_fair_arbiter.v

minor update

2021-09-06 23:44:31 -07:00

VX_fifo_queue.v

code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00

VX_find_first.v

code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00

VX_fixed_arbiter.v

Disabling tracing on library

2021-08-12 01:55:52 -07:00

VX_index_buffer.v

code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00

VX_index_queue.v

code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00

VX_lzc.v

code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00

VX_matrix_arbiter.v

Disabling tracing on library

2021-08-12 01:55:52 -07:00

VX_multiplier.v

Adding Vortex Yosys build support

2021-09-08 23:04:33 -04:00

VX_mux.v

Disabling tracing on library

2021-08-12 01:55:52 -07:00

VX_onehot_encoder.v

LKG Build (reset network update -fmax=236 mhz 4c)

2021-08-23 01:59:22 -07:00

VX_onehot_mux.v

Disabling tracing on library

2021-08-12 01:55:52 -07:00

VX_pending_size.v

code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00

VX_pipe_register.v

Disabling tracing on library

2021-08-12 01:55:52 -07:00

VX_priority_encoder.v

critical path optimizations

2021-09-15 04:50:45 -07:00

VX_reset_relay.v

LKG Build (reset network update -fmax=236 mhz 4c)

2021-08-23 01:59:22 -07:00

VX_rr_arbiter.v

Disabling tracing on library

2021-08-12 01:55:52 -07:00

VX_scan.v

Updated README and synthesis scripts

2021-09-22 07:50:47 -07:00

VX_scope.v

fixed Verilator error

2021-08-13 19:33:12 -07:00

VX_serial_div.v

Disabling tracing on library

2021-08-12 01:55:52 -07:00

VX_shift_register.v

minor updates

2021-09-05 23:05:21 -07:00

VX_skid_buffer.v

code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00

VX_sp_ram.v

code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00

VX_stream_arbiter.v

critical path optimizations

2021-09-15 04:50:45 -07:00

VX_stream_demux.v

code refactoring for Vivado, sv2v, and yosys compatibility

2021-09-27 08:55:10 -04:00