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1ea738ed26
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lkg build
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2021-06-25 16:28:10 -07:00 |
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2372067817
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minor update
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2021-06-22 09:30:36 -07:00 |
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c331da5ff7
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adding fast DPI implemntation of imul and idiv
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2021-06-22 09:02:41 -07:00 |
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6213b1a910
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vortex runtime console out implementation
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2021-06-15 04:01:44 -04:00 |
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fe86fd7936
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xMerge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-06-13 21:44:46 -04:00 |
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03406c0a3f
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project tests refactoring
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2021-06-13 17:42:04 -07:00 |
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76c4909ae9
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minor update
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2021-06-12 02:22:01 -04:00 |
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a315d0087d
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opae_sim buffer index allocation bug fix
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2021-06-11 15:20:02 -07:00 |
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78a452ea6e
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minor update
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2021-06-11 12:54:10 -07:00 |
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104da0c238
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kernels update
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2021-06-11 06:21:25 -04:00 |
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3cc1190cd7
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CSRs I/O refactoring
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2021-06-11 03:08:07 -07:00 |
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ba4f705807
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minor update
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2021-06-06 14:04:15 -07:00 |
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ff911d7f8d
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minor update (renaming stress -> mstress)
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2021-06-06 14:03:46 -07:00 |
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3071fb7a29
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adding support for non-cacheable memory addressing
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2021-06-06 13:35:55 -07:00 |
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84391c1a06
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minor update
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2021-06-04 20:46:34 -07:00 |
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df7d91d690
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more testing
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2021-05-26 15:29:39 -07:00 |
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b3e54e66f8
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fixed compiler warnings
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2021-05-23 10:54:06 -07:00 |
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3e88a71801
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minor update
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2021-05-06 08:55:46 -07:00 |
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bde6a69ea0
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adding support for multi-banks memory bus
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2021-05-04 07:32:03 -07:00 |
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bdbf99c5b0
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minor update
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2021-05-03 12:53:15 -07:00 |
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76f5531b58
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adding stress test pre-built kernel
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2021-05-03 12:44:36 -07:00 |
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ba16e88eab
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stress test update
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2021-05-03 12:24:41 -07:00 |
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c1f40e081d
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adding stress test
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2021-05-03 03:37:28 -07:00 |
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fc7c8e1639
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driver tests updates
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2021-05-02 12:12:59 -07:00 |
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d504adb236
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afu mem controller refactoring
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2021-05-01 08:39:52 -07:00 |
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95f057bc2e
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fpga build refactoring
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2021-04-29 06:17:28 -07:00 |
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2216a3059d
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minor update
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2021-04-27 05:52:01 -04:00 |
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64848788a1
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minor update
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2021-04-26 20:34:28 -07:00 |
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8543e3a8bf
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code refactoring
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2021-04-26 02:34:21 -07:00 |
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8410c49f53
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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0615e7481a
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minor update
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2021-04-24 03:06:24 -04:00 |
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cad21a4b92
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minor update
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2021-04-24 01:17:38 -04:00 |
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4cb98a25a7
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enabling 128-bit dram bus
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2021-04-24 00:31:27 -04:00 |
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3a266fc792
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adding compiler tests to regression suite
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2021-03-09 05:01:56 -08:00 |
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ad11bdfc87
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fix warnings
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2021-03-09 04:58:00 -08:00 |
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c0abd6ef3f
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Aligned memory allocation workaround for PACE clusters
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2021-03-09 03:25:45 -08:00 |
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66ea340d05
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Fix RAM memory deallocation
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2021-03-09 01:52:56 -08:00 |
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907e6868cd
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simx refactoring, fixed simple.hex, compatibility with rtlsim and vlsim complete, added to regression suite
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2021-03-08 23:58:33 -08:00 |
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71e9745e68
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simx lkg build
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2021-03-08 08:34:02 -08:00 |
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8eac091fb5
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simX floating-point fixes and refactoring
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2021-03-08 03:44:08 -08:00 |
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062d02ddce
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-03-04 20:51:03 -08:00 |
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8a86bddd3e
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fixed simX multicore support, added shared memory
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2021-03-04 20:45:27 -08:00 |
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41f09ffb55
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minor update - allow independent driver cleanup
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2021-02-28 18:19:26 -08:00 |
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e6bb8ccd94
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-02-28 17:21:19 -08:00 |
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9fda618815
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minor typo
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2021-02-28 01:58:41 -08:00 |
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Blaise Tine
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a8452483fe
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simX refactoring
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2021-02-27 02:27:19 -08:00 |
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Blaise Tine
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700f9eea19
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moving MUL unit into ALU unit
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2021-02-23 13:49:02 -08:00 |
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Blaise Tine
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6c1dc96626
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simX refactoring + removed oldRTL + CSR updates
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2021-02-06 12:52:54 -08:00 |
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Blaise Tine
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778453e43f
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remove unused code from kernel binaries, spawn_kernel optimization using shift instead of division
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2021-02-04 17:35:57 -05:00 |
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Blaise Tine
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b047f589d6
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runtime instrinsics refactoring using RISC-V custom instruction assmebly directives
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2021-02-04 15:15:20 -05:00 |
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