wgulian3
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61803741f8
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Merge branch 'master' into fpga_synthesis
# Conflicts:
# rtl/VX_back_end.v
# rtl/VX_gpr_stage.v
# rtl/VX_writeback.v
# rtl/simulate/test_bench.cpp
# rtl/simulate/test_bench.h
# runtime/mains/dev/Makefile
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2020-02-18 03:34:38 -05:00 |
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felsabbagh3
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3a45375596
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Fixed Verilator
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2020-02-17 19:36:00 -08:00 |
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wgulian3
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8318aff69f
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Support exec multi-cycle for div/mul
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2020-02-13 13:17:46 -05:00 |
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wgulian3
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8d20b52ea2
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Cleanup imports of VX_define
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2020-02-04 10:57:32 -05:00 |
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wgulian3
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e9cdc6e5af
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SystemVerilog tweaks to appease Quartus and make Quartus synthesis work
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2020-01-24 06:10:24 -05:00 |
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Lyons, Ethan Tyler
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b0f685c2e2
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Add files via upload
ICache_In_Place
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2019-11-08 10:55:08 -05:00 |
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Savan Roshan
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e4ee2a9cbd
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Parameterization working
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2019-11-07 00:14:46 -05:00 |
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Savan Roshan
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8468e7d4d9
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Added prefix DCACHE_
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2019-11-05 08:33:38 -05:00 |
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Savan Roshan
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1db160a289
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Fixed parameterization
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2019-11-04 14:32:02 -05:00 |
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felsabbagh3
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3b49b82c46
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GPR ASIC Working
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2019-10-29 23:20:16 -04:00 |
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felsabbagh3
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a8d063e9ad
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Synthesis Cleanup 1
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2019-10-28 13:43:12 -04:00 |
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felsabbagh3
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0ee74bc566
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migrated 100% to modelsim
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2019-10-27 20:08:44 -04:00 |
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felsabbagh3
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1181af1df2
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Modelsim basic sim
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2019-10-26 00:34:57 -04:00 |
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felsabbagh3
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01efe02e8b
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CACHE WORKING just needs lb/sb
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2019-10-25 03:03:09 -04:00 |
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felsabbagh3
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1e648c5819
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FIxed first circular issue
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2019-10-24 10:38:04 -04:00 |
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felsabbagh3
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9d8273afe4
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Finished Cache Integration
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2019-10-22 06:02:08 -04:00 |
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felsabbagh3
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b7af8c3f34
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Integrated Shared Memory
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2019-10-22 05:03:47 -04:00 |
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felsabbagh3
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1bfafca896
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Cleanup before integration
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2019-10-22 03:03:17 -04:00 |
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felsabbagh3
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0672389edc
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fix
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2019-10-21 12:16:17 -04:00 |
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felsabbagh3
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84f5ccb484
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Added CSR TID/WID reads
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2019-10-21 02:10:05 -04:00 |
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felsabbagh3
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629ed3f8f9
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Before ISA2.0
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2019-10-18 04:15:34 -04:00 |
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felsabbagh3
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559c64cb36
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Cleanup
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2019-10-18 02:20:38 -04:00 |
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felsabbagh3
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505bbc20c8
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Removed FWD
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2019-10-18 02:01:39 -04:00 |
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felsabbagh3
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95047fcadc
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Rename Stage that removes the need for forwarding
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2019-10-17 00:48:54 -04:00 |
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felsabbagh3
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ee83e6d8c8
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Moved GPR to back-end
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2019-10-14 19:08:32 -04:00 |
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felsabbagh3
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fb3bc60189
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Finalized GPR with 3-Port Structure
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2019-09-11 14:53:32 -04:00 |
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felsabbagh3
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ecf81336db
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Finished FE and BE high-level
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2019-09-08 19:28:53 -04:00 |
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felsabbagh3
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981bf0afe5
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FE Done
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2019-09-08 18:36:47 -04:00 |
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felsabbagh3
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ad45758a35
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Before Fetch->FE
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2019-09-08 18:09:11 -04:00 |
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felsabbagh3
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c310e7381f
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Icache interface
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2019-09-08 17:36:09 -04:00 |
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felsabbagh3
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5e6804703f
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Decode in FE
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2019-09-08 17:24:51 -04:00 |
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felsabbagh3
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ac9b06bf7d
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Before FE BE abstraction
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2019-09-08 16:21:37 -04:00 |
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felsabbagh3
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fe09aafbb4
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Interface Checkpoint 2 - Remove Lints
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2019-09-05 19:32:37 -04:00 |
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felsabbagh3
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2d0e41db63
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checkpoint: Added icache struct
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2019-09-03 16:19:06 -04:00 |
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felsabbagh3
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d7afef04a9
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Sim Work miss
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2019-05-18 23:42:55 +04:00 |
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felsabbagh3
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48468ed26a
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Proper SIMT with fine-grain scheduler implemented
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2019-05-10 00:49:54 -07:00 |
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felsabbagh3
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96dac5e1ce
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Warp + Context Aware Design - Global Stalling
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2019-05-08 16:32:49 -07:00 |
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felsabbagh3
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a6c13bc38c
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Inefficient context aware desgin
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2019-05-08 15:55:06 -07:00 |
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felsabbagh3
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f21eaec79f
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Provisioned SM
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2019-04-05 19:25:54 -04:00 |
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felsabbagh3
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c83ef94d02
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1 WARP 2 THREADS WORKING
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2019-03-31 05:02:55 -04:00 |
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felsabbagh3
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a3a3b21de7
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Using verilog For-loops + Passing all tests
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2019-03-30 22:09:03 -04:00 |
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felsabbagh3
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99a0792a0c
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Passing all tests with 2 threads
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2019-03-30 03:54:20 -04:00 |
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felsabbagh3
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d02c3d25b7
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sync
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2019-03-27 13:52:13 -04:00 |
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felsabbagh3
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68f3ba84e5
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Added HW threads - Infinite loop + fixed valid
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2019-03-27 03:53:59 -04:00 |
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felsabbagh3
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9b42e79dcf
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Added HW threads - Infinite loop
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2019-03-27 03:44:14 -04:00 |
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felsabbagh3
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cc0fb0eece
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better use of valid signal
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2019-03-27 00:07:59 -04:00 |
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felsabbagh3
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7a528c5ef2
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Packing data wires + ALU module
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2019-03-26 19:17:11 -04:00 |
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