Codetector
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072c89c433
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Merge branch 'fpga_synthesis' into fix_cache_m10k
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2020-02-19 16:03:23 -05:00 |
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wgulian3
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5dadeffac8
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fix project.tcl
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2020-02-19 14:20:58 -05:00 |
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wgulian3
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3b60c10460
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Merge branch 'fpga_synthesis' of github.gatech.edu:casl/Vortex into fpga_synthesis
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2020-02-19 01:04:55 -05:00 |
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wgulian3
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3423e3189f
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Fix e2e building issues and increase division pipeline length
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2020-02-19 01:04:48 -05:00 |
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wgulian3
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3e68c8bcf5
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verilator does not support delayed assignment in a loop
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2020-02-18 13:38:17 -05:00 |
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wgulian3
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e76d05f7ce
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Fix issues quartus synthesis issues
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2020-02-18 13:24:18 -05:00 |
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wgulian3
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d71f8fcc73
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Fix divide edge case in verilator and move divide modules out of SYN_FUNC block within alu.
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2020-02-18 13:02:46 -05:00 |
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wgulian3
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a32d654263
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Merge branch 'master' into fpga_synthesis
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2020-02-18 03:35:12 -05:00 |
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wgulian3
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61803741f8
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Merge branch 'master' into fpga_synthesis
# Conflicts:
# rtl/VX_back_end.v
# rtl/VX_gpr_stage.v
# rtl/VX_writeback.v
# rtl/simulate/test_bench.cpp
# rtl/simulate/test_bench.h
# runtime/mains/dev/Makefile
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2020-02-18 03:34:38 -05:00 |
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felsabbagh3
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28ce40eebf
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fixed make w + vx_gpr_stage csr schedule
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2020-02-18 00:26:44 -08:00 |
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felsabbagh3
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be66e51613
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Added CSRs, some Load unit tests are failing
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2020-02-17 22:22:27 -08:00 |
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felsabbagh3
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a0f3f67426
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Fixed double printing in ::io_handler
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2020-02-17 19:47:55 -08:00 |
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felsabbagh3
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551c4aa2e9
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2020-02-17 19:36:17 -08:00 |
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felsabbagh3
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3a45375596
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Fixed Verilator
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2020-02-17 19:36:00 -08:00 |
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Blaise Tine
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3aa4c26eb9
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minor fix
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2020-02-17 20:36:16 -05:00 |
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Blaise Tine
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90c3813340
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fixed all C++ extra + pedantic errors
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2020-02-17 15:02:06 -05:00 |
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wgulian3
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4184980188
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verilator: run all riscv tests
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2020-02-13 13:50:57 -05:00 |
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wgulian3
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e662ef4134
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Fix verilator
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2020-02-13 13:42:43 -05:00 |
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wgulian3
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86bfa4d1e4
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Fix verilator
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2020-02-13 13:18:06 -05:00 |
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wgulian3
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8318aff69f
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Support exec multi-cycle for div/mul
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2020-02-13 13:17:46 -05:00 |
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codetector
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ded06bcd12
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ram m10k fix
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2020-02-11 09:57:32 -05:00 |
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wgulian3
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c1bd731d7f
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Add ram async clear port fix for fpga RAM inference
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2020-02-06 13:07:50 -05:00 |
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wgulian3
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9c7a9d88cf
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Replace div/rem expressions with divider modules in preparation for pipelining
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2020-02-04 11:54:06 -05:00 |
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wgulian3
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0211ca4add
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Add compat divide module and tb
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2020-02-04 10:59:05 -05:00 |
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wgulian3
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8d20b52ea2
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Cleanup imports of VX_define
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2020-02-04 10:57:32 -05:00 |
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Elsabbagh, Fares Ehab Mohamed Abouelnasr
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0e0ea52568
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Merge pull request #1 from casl/OPAE
opae
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2020-01-30 13:45:05 -08:00 |
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Apurve Chawda
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2eed4e68be
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Create opae_setup.sh
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2020-01-30 16:41:37 -05:00 |
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Tine, Blaise
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cd07b508fa
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Update README.md
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2020-01-29 15:39:33 -05:00 |
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wgulian3
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d727404f3b
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timing analysis tcl
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2020-01-28 04:09:00 -05:00 |
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wgulian3
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4158b29f29
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Fancier SDC file
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2020-01-28 02:20:13 -05:00 |
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wgulian3
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a6e74f589e
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Update files
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2020-01-27 20:35:45 -05:00 |
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Tine, Blaise
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ca283f39eb
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Update README.md
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2020-01-27 03:42:36 -05:00 |
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Tine, Blaise
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9b66bb4ed4
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Update README.md
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2020-01-27 01:46:31 -05:00 |
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wgulian3
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12a4136464
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quartus makefile: Support custom Quartus root location
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2020-01-24 18:42:03 -05:00 |
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wgulian3
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e9cdc6e5af
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SystemVerilog tweaks to appease Quartus and make Quartus synthesis work
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2020-01-24 06:10:24 -05:00 |
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Blaise Tine
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229d76ff23
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update
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2020-01-22 00:56:03 -05:00 |
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Blaise Tine
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383bc15794
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update
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2020-01-22 00:49:23 -05:00 |
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Blaise Tine
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df435ffa97
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update README
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2020-01-22 00:47:57 -05:00 |
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Blaise Tine
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43d5612a6b
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updated README
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2020-01-21 21:23:00 -05:00 |
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Blaise Tine
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759349f2bf
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updated README and Makefile environment settings
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2020-01-21 21:21:56 -05:00 |
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Tine, Blaise
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60f0cfe215
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Create LICENSE
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2020-01-11 11:00:37 -05:00 |
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Tine, Blaise
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db3a9e4f73
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Update README.md
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2020-01-11 10:59:46 -05:00 |
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Tine, Blaise
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ad7f2518ed
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Delete .DS_Store
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2020-01-11 10:47:22 -05:00 |
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Tine, Blaise
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e38bdcdb33
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Delete sftp-config.json
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2020-01-11 10:46:57 -05:00 |
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Tine, Blaise
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0aa5f1fb40
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Delete results.txt
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2020-01-11 10:46:48 -05:00 |
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Tine, Blaise
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0c886a8989
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Update README.md
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2020-01-11 10:40:26 -05:00 |
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Blaise Tine
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35088b6e1a
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update
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2020-01-11 10:06:14 -05:00 |
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Tine, Blaise
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33c882f9e8
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Delete dummy.txt
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2020-01-11 09:41:28 -05:00 |
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Tine, Blaise
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9ec835c8f7
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Delete stylesheet.css
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2020-01-11 09:41:12 -05:00 |
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Tine, Blaise
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e1bd0e568f
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Delete normalize.css
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2020-01-11 09:40:58 -05:00 |
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