 Lingjun Zhu
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50d567d70c
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Removed unnessary Verilog files, linked memory tech files, having problem with memory instatiation
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2019-10-28 14:49:55 -04:00 |
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felsabbagh3
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b7af8c3f34
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Integrated Shared Memory
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2019-10-22 05:03:47 -04:00 |
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Lingjun Zhu
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93531715bb
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Created a testbench and simulated the read/write of the register file
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2019-10-18 22:55:34 -04:00 |
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felsabbagh3
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9a9afbbb6b
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Updated makefile
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2019-10-16 19:56:11 -04:00 |
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felsabbagh3
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0690043a43
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Still giving sc_time_stamp error
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2019-10-16 19:45:21 -04:00 |
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felsabbagh3
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8bc3b8b0a5
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Need to link SystemC for sc_time_stamp()
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2019-10-14 23:25:14 -04:00 |
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Lingjun Zhu
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5680b997b5
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Generate LIB files for rf2_32x128_wm1
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2019-10-14 17:08:18 -04:00 |
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Lingjun Zhu
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b9d2e09d78
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Move the memory models from Cache_Progress to Master branch
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2019-10-13 13:13:42 -04:00 |
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