added altera fpu modules

2020-08-05 15:53:59 -07:00
parent d8bdaa2b4e
commit ffd9515881
48 changed files with 8888 additions and 459 deletions
--- a/hw/syn/quartus/project.sdc
+++ b/hw/syn/quartus/project.sdc
@@ -1,6 +1,6 @@
 set_time_format -unit ns -decimal_places 3

-create_clock -name {clk} -period "200 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]
+create_clock -name {clk} -period "300 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]

 derive_pll_clocks -create_base_clocks
 derive_clock_uncertainty