From ffd9515881f5a7941509286fd6a8b79becd8bff2 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Wed, 5 Aug 2020 15:53:59 -0700 Subject: [PATCH] added altera fpu modules --- hw/opae/gen_sources.sh | 16 +- hw/opae/sources_1c.txt | 1 + hw/rtl/VX_define.vh | 27 +- hw/rtl/VX_gpr_stage.v | 2 +- hw/rtl/VX_lsu_unit.v | 4 +- hw/rtl/VX_mul_unit.v | 4 +- hw/rtl/VX_scheduler.v | 2 +- hw/rtl/VX_warp_sched.v | 15 +- hw/rtl/VX_writeback.v | 24 +- hw/rtl/fp_cores/VX_fp_fpga.v | 275 ++- hw/rtl/fp_cores/VX_fp_noncomp.v | 243 +++ hw/rtl/fp_cores/VX_fp_type.v | 19 + hw/rtl/fp_cores/VX_fpnew.v | 32 +- hw/rtl/fp_cores/altera/VX_fp_add.v | 80 + hw/rtl/fp_cores/altera/VX_fp_div.v | 49 + hw/rtl/fp_cores/altera/VX_fp_ftoi.v | 47 + hw/rtl/fp_cores/altera/VX_fp_ftou.v | 47 + hw/rtl/fp_cores/altera/VX_fp_itof.v | 47 + hw/rtl/fp_cores/altera/VX_fp_madd.v | 145 ++ hw/rtl/fp_cores/altera/VX_fp_msub.v | 145 ++ hw/rtl/fp_cores/altera/VX_fp_mul.v | 80 + hw/rtl/fp_cores/altera/VX_fp_sqrt.v | 47 + hw/rtl/fp_cores/altera/VX_fp_sub.v | 80 + hw/rtl/fp_cores/altera/VX_fp_utof.v | 47 + hw/rtl/fp_cores/altera/acl_fp_add.v | 67 - hw/rtl/fp_cores/altera/acl_fp_div.sv | 1605 +++++++++++++++++ ...p_div_memoryC0_uid112_invTables_lutmem.hex | 514 ++++++ ...p_div_memoryC1_uid115_invTables_lutmem.hex | 514 ++++++ ...p_div_memoryC2_uid118_invTables_lutmem.hex | 514 ++++++ hw/rtl/fp_cores/altera/acl_fp_ftoi.sv | 518 ++++++ hw/rtl/fp_cores/altera/acl_fp_ftou.sv | 503 ++++++ hw/rtl/fp_cores/altera/acl_fp_itof.sv | 522 ++++++ hw/rtl/fp_cores/altera/acl_fp_msub.v | 63 - hw/rtl/fp_cores/altera/acl_fp_mul.v | 67 - hw/rtl/fp_cores/altera/acl_fp_nmadd.v | 63 - hw/rtl/fp_cores/altera/acl_fp_sqrt.sv | 1128 ++++++++++++ ..._sqrt_memoryC0_uid62_sqrtTables_lutmem.hex | 258 +++ ..._sqrt_memoryC1_uid65_sqrtTables_lutmem.hex | 258 +++ ..._sqrt_memoryC2_uid68_sqrtTables_lutmem.hex | 258 +++ hw/rtl/fp_cores/altera/acl_fp_sub.v | 67 - hw/rtl/fp_cores/altera/acl_fp_utof.sv | 486 +++++ hw/rtl/fp_cores/altera/dspba_library_ver.sv | 392 ++++ hw/rtl/fp_cores/altera/generate.sh | 25 + hw/rtl/interfaces/VX_cmt_to_issue_if.v | 12 +- hw/rtl/libs/VX_divide.v | 3 +- hw/rtl/libs/VX_multiplier.v | 2 - hw/rtl/libs/VX_shift_register.v | 28 +- hw/syn/quartus/project.sdc | 2 +- 48 files changed, 8888 insertions(+), 459 deletions(-) create mode 100644 hw/rtl/fp_cores/VX_fp_noncomp.v create mode 100644 hw/rtl/fp_cores/VX_fp_type.v create mode 100644 hw/rtl/fp_cores/altera/VX_fp_add.v create mode 100644 hw/rtl/fp_cores/altera/VX_fp_div.v create mode 100644 hw/rtl/fp_cores/altera/VX_fp_ftoi.v create mode 100644 hw/rtl/fp_cores/altera/VX_fp_ftou.v create mode 100644 hw/rtl/fp_cores/altera/VX_fp_itof.v create mode 100644 hw/rtl/fp_cores/altera/VX_fp_madd.v create mode 100644 hw/rtl/fp_cores/altera/VX_fp_msub.v create mode 100644 hw/rtl/fp_cores/altera/VX_fp_mul.v create mode 100644 hw/rtl/fp_cores/altera/VX_fp_sqrt.v create mode 100644 hw/rtl/fp_cores/altera/VX_fp_sub.v create mode 100644 hw/rtl/fp_cores/altera/VX_fp_utof.v delete mode 100644 hw/rtl/fp_cores/altera/acl_fp_add.v create mode 100644 hw/rtl/fp_cores/altera/acl_fp_div.sv create mode 100644 hw/rtl/fp_cores/altera/acl_fp_div_memoryC0_uid112_invTables_lutmem.hex create mode 100644 hw/rtl/fp_cores/altera/acl_fp_div_memoryC1_uid115_invTables_lutmem.hex create mode 100644 hw/rtl/fp_cores/altera/acl_fp_div_memoryC2_uid118_invTables_lutmem.hex create mode 100644 hw/rtl/fp_cores/altera/acl_fp_ftoi.sv create mode 100644 hw/rtl/fp_cores/altera/acl_fp_ftou.sv create mode 100644 hw/rtl/fp_cores/altera/acl_fp_itof.sv delete mode 100644 hw/rtl/fp_cores/altera/acl_fp_msub.v delete mode 100644 hw/rtl/fp_cores/altera/acl_fp_mul.v delete mode 100644 hw/rtl/fp_cores/altera/acl_fp_nmadd.v create mode 100644 hw/rtl/fp_cores/altera/acl_fp_sqrt.sv create mode 100644 hw/rtl/fp_cores/altera/acl_fp_sqrt_memoryC0_uid62_sqrtTables_lutmem.hex create mode 100644 hw/rtl/fp_cores/altera/acl_fp_sqrt_memoryC1_uid65_sqrtTables_lutmem.hex create mode 100644 hw/rtl/fp_cores/altera/acl_fp_sqrt_memoryC2_uid68_sqrtTables_lutmem.hex delete mode 100644 hw/rtl/fp_cores/altera/acl_fp_sub.v create mode 100644 hw/rtl/fp_cores/altera/acl_fp_utof.sv create mode 100644 hw/rtl/fp_cores/altera/dspba_library_ver.sv create mode 100755 hw/rtl/fp_cores/altera/generate.sh diff --git a/hw/opae/gen_sources.sh b/hw/opae/gen_sources.sh index 3f6b5f42..0120d34f 100755 --- a/hw/opae/gen_sources.sh +++ b/hw/opae/gen_sources.sh @@ -1,12 +1,20 @@ #!/bin/bash -dir_list='../rtl/libs ../rtl/cache ../rtl/interfaces ../rtl ../rtl/fp_cores/fpnew/src/common_cells/include ../rtl/fp_cores ../rtl/fp_cores/altera ../rtl/fp_cores/fpnew/src/common_cells/src ../rtl/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl ../rtl/fp_cores/fpnew/src' +dir_list='../rtl/libs ../rtl/cache ../rtl/interfaces ../rtl ../rtl/fp_cores/fpnew/src/common_cells/include ../rtl/fp_cores ../rtl/fp_cores/altera' +exclude_list='VX_fpnew.v' # read design sources for dir in $dir_list; do echo "+incdir+$dir" - for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f) - do - echo $file + for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f); do + exclude=0 + for fe in $exclude_list; do + if [[ $file =~ $fe ]]; then + exclude=1 + fi + done + if [[ $exclude == 0 ]]; then + echo $file + fi done done \ No newline at end of file diff --git a/hw/opae/sources_1c.txt b/hw/opae/sources_1c.txt index b40f7162..a07c4d79 100644 --- a/hw/opae/sources_1c.txt +++ b/hw/opae/sources_1c.txt @@ -1,6 +1,7 @@ +define+NUM_CORES=1 #+define+SCOPE ++define+SYNTHESIS #+define+DBG_PRINT_CORE_ICACHE #+define+DBG_PRINT_CORE_DCACHE diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index d61b001c..8c684ddf 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -38,9 +38,16 @@ /////////////////////////////////////////////////////////////////////////////// -`define LATENCY_IDIV 24 +`define LATENCY_IDIV 22 `define LATENCY_IMUL 2 +`define LATENCY_FDIV 16 +`define LATENCY_FSQRT 10 +`define LATENCY_FTOI 5 +`define LATENCY_FTOU 4 +`define LATENCY_ITOF 8 +`define LATENCY_UTOF 7 + `define LATENCY_FMULADD 2 `define LATENCY_FDIVSQRT 2 `define LATENCY_FCONV 2 @@ -193,6 +200,12 @@ `define FRM_RMM 3'b100 // round to nearest max magnitude `define FRM_DYN 3'b111 // dynamic mode `define FRM_BITS 3 + +`define FFG_NX 0 // inexact +`define FFG_UF 1 // underflow +`define FFG_OF 2 // overflow +`define FFG_DZ 3 // division by zero +`define FFG_NV 4 // invalid `define FFG_BITS 5 `define GPU_TMC 3'h0 @@ -415,6 +428,16 @@ typedef struct packed { logic [31:0] curr_PC; logic [`NR_BITS-1:0] rd; logic wb; -} is_data_t; +} issue_data_t; + +typedef struct packed { + logic is_normal; + logic is_zero; + logic is_subnormal; + logic is_inf; + logic is_nan; + logic is_signaling; + logic is_quiet; +} fp_type_t; `endif diff --git a/hw/rtl/VX_gpr_stage.v b/hw/rtl/VX_gpr_stage.v index 17992b4d..9e49ca57 100644 --- a/hw/rtl/VX_gpr_stage.v +++ b/hw/rtl/VX_gpr_stage.v @@ -16,7 +16,7 @@ module VX_gpr_stage #( wire [`NUM_THREADS-1:0][31:0] rs1_data; wire [`NUM_THREADS-1:0][31:0] rs2_data; - wire [`NW_BITS+`NR_BITS-1:0] raddr1; + wire [`NW_BITS+`NR_BITS-1:0] raddr1; VX_gpr_ram gpr_ram ( .clk (clk), diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v index 2074d44e..bf086fbd 100644 --- a/hw/rtl/VX_lsu_unit.v +++ b/hw/rtl/VX_lsu_unit.v @@ -86,7 +86,7 @@ module VX_lsu_unit #( .reset (reset), .stall (stall_in), .flush (0), - .in ({lsu_req_if.valid, lsu_req_if.warp_num, lsu_req_if.thread_mask, lsu_req_if.issue_tag, full_address, mem_req_sext, lsu_req_if.rw, mem_req_addr, mem_req_offset, mem_req_byteen, mem_req_data, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.curr_PC}), + .in ({lsu_req_if.valid, lsu_req_if.warp_num, lsu_req_if.thread_mask, lsu_req_if.issue_tag, full_address, mem_req_sext, lsu_req_if.rw, mem_req_addr, mem_req_offset, mem_req_byteen, mem_req_data, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.curr_PC}), .out ({use_valid, use_warp_num, use_thread_mask, use_issue_tag, use_address, use_req_sext, use_req_rw, use_req_addr, use_req_offset, use_req_byteen, use_req_data, use_rd, use_wb, use_pc}) ); @@ -126,7 +126,7 @@ module VX_lsu_unit #( mem_rsp_rd_buf [use_issue_tag] <= use_rd; end if (dcache_rsp_fire) begin - mem_rsp_mask_buf [rsp_issue_tag] <= mem_rsp_mask_n; + mem_rsp_mask_buf [rsp_issue_tag] <= mem_rsp_mask_n; mem_rsp_data_all_buf [rsp_issue_tag] <= mem_rsp_data_all | mem_rsp_data_curr; end end diff --git a/hw/rtl/VX_mul_unit.v b/hw/rtl/VX_mul_unit.v index 691f30ae..36b46bba 100644 --- a/hw/rtl/VX_mul_unit.v +++ b/hw/rtl/VX_mul_unit.v @@ -104,7 +104,7 @@ module VX_mul_unit #( VX_shift_register #( .DATAW(1 + `ISTAG_BITS + 1), .DEPTH(`LATENCY_IMUL) - ) mul_delay ( + ) mul_shift_reg ( .clk(clk), .reset(reset), .enable(~stall_mul), @@ -115,7 +115,7 @@ module VX_mul_unit #( VX_shift_register #( .DATAW(1 + `ISTAG_BITS + `NUM_THREADS), .DEPTH(`LATENCY_IDIV) - ) div_delay ( + ) div_shift_reg ( .clk(clk), .reset(reset), .enable(~stall_div), diff --git a/hw/rtl/VX_scheduler.v b/hw/rtl/VX_scheduler.v index 22afdec1..d922e768 100644 --- a/hw/rtl/VX_scheduler.v +++ b/hw/rtl/VX_scheduler.v @@ -67,7 +67,7 @@ module VX_scheduler #( wire issue_fire = decode_if.valid && ~stall; VX_cam_buffer #( - .DATAW ($bits(is_data_t)), + .DATAW ($bits(issue_data_t)), .SIZE (`ISSUEQ_SIZE), .RPORTS (`NUM_EXS) ) issue_buffer ( diff --git a/hw/rtl/VX_warp_sched.v b/hw/rtl/VX_warp_sched.v index 04c2d80e..80eda9f7 100644 --- a/hw/rtl/VX_warp_sched.v +++ b/hw/rtl/VX_warp_sched.v @@ -123,12 +123,12 @@ module VX_warp_sched #( thread_masks[join_if.warp_num] <= join_tm; didnt_split <= 0; end else if (warp_ctl_if.is_split) begin - warp_stalled[warp_ctl_if.warp_num] <= 0; + warp_stalled[warp_ctl_if.warp_num] <= 0; if (warp_ctl_if.do_split) begin thread_masks[warp_ctl_if.warp_num] <= warp_ctl_if.split_new_mask; - didnt_split <= 0; + didnt_split <= 0; end else begin - didnt_split <= 1; + didnt_split <= 1; end end @@ -206,11 +206,8 @@ module VX_warp_sched #( genvar i; for (i = 0; i < `NUM_WARPS; i++) begin - wire correct_warp_s = (i == warp_ctl_if.warp_num); - wire correct_warp_j = (i == join_if.warp_num); - - wire push = (warp_ctl_if.is_split && warp_ctl_if.do_split) && correct_warp_s; - wire pop = join_if.is_join && correct_warp_j; + wire push = warp_ctl_if.is_split && warp_ctl_if.do_split && (i == warp_ctl_if.warp_num); + wire pop = join_if.is_join && (i == join_if.warp_num); VX_ipdom_stack #( .WIDTH(1+32+`NUM_THREADS), @@ -234,7 +231,7 @@ module VX_warp_sched #( assign real_schedule = schedule && !warp_stalled[warp_to_schedule] && !total_barrier_stall[warp_to_schedule] && !warp_lock[0]; - assign global_stall = (stall || wstall_this_cycle || hazard || !real_schedule || join_if.is_join); + assign global_stall = stall || wstall_this_cycle || hazard || !real_schedule || join_if.is_join; assign scheduled_warp = !(wstall_this_cycle || hazard || !real_schedule || join_if.is_join) && !reset; diff --git a/hw/rtl/VX_writeback.v b/hw/rtl/VX_writeback.v index 8519b9f7..60e86440 100644 --- a/hw/rtl/VX_writeback.v +++ b/hw/rtl/VX_writeback.v @@ -25,8 +25,8 @@ module VX_writeback #( reg [31:0] wb_curr_PC_table [`ISSUEQ_SIZE-1:0]; reg [`NR_BITS-1:0] wb_rd_table [`ISSUEQ_SIZE-1:0]; - reg [`ISSUEQ_SIZE-1:0] wb_pending; - reg [`ISSUEQ_SIZE-1:0] wb_pending_n; + reg [`ISSUEQ_SIZE-1:0] wb_valid_table; + reg [`ISSUEQ_SIZE-1:0] wb_valid_table_n; reg [`ISTAG_BITS-1:0] wb_index; wire [`ISTAG_BITS-1:0] wb_index_n; @@ -35,40 +35,40 @@ module VX_writeback #( wire wb_valid_n; always @(*) begin - wb_pending_n = wb_pending; + wb_valid_table_n = wb_valid_table; if (wb_valid) begin - wb_pending_n[wb_index] = 0; + wb_valid_table_n[wb_index] = 0; end if (alu_commit_if.valid) begin - wb_pending_n [alu_commit_if.issue_tag] = cmt_to_issue_if.alu_data.wb; + wb_valid_table_n [alu_commit_if.issue_tag] = cmt_to_issue_if.alu_data.wb; end if (lsu_commit_if.valid) begin - wb_pending_n [lsu_commit_if.issue_tag] = cmt_to_issue_if.lsu_data.wb; + wb_valid_table_n [lsu_commit_if.issue_tag] = cmt_to_issue_if.lsu_data.wb; end if (csr_commit_if.valid) begin - wb_pending_n [csr_commit_if.issue_tag] = cmt_to_issue_if.csr_data.wb; + wb_valid_table_n [csr_commit_if.issue_tag] = cmt_to_issue_if.csr_data.wb; end if (mul_commit_if.valid) begin - wb_pending_n [mul_commit_if.issue_tag] = cmt_to_issue_if.mul_data.wb; + wb_valid_table_n [mul_commit_if.issue_tag] = cmt_to_issue_if.mul_data.wb; end if (fpu_commit_if.valid) begin - wb_pending_n [fpu_commit_if.issue_tag] = cmt_to_issue_if.fpu_data.wb; + wb_valid_table_n [fpu_commit_if.issue_tag] = cmt_to_issue_if.fpu_data.wb; end end VX_priority_encoder #( .N(`ISSUEQ_SIZE) ) wb_select ( - .data_in (wb_pending_n), + .data_in (wb_valid_table_n), .data_out (wb_index_n), .valid_out (wb_valid_n) ); always @(posedge clk) begin if (reset) begin - wb_pending <= 0; + wb_valid_table <= 0; wb_index <= 0; wb_valid <= 0; end else begin @@ -112,7 +112,7 @@ module VX_writeback #( wb_rd_table [fpu_commit_if.issue_tag] <= cmt_to_issue_if.fpu_data.rd; end - wb_pending <= wb_pending_n; + wb_valid_table <= wb_valid_table_n; wb_index <= wb_index_n; wb_valid <= wb_valid_n && writeback_if.ready; end diff --git a/hw/rtl/fp_cores/VX_fp_fpga.v b/hw/rtl/fp_cores/VX_fp_fpga.v index e120a4a0..fc35d9db 100644 --- a/hw/rtl/fp_cores/VX_fp_fpga.v +++ b/hw/rtl/fp_cores/VX_fp_fpga.v @@ -1,4 +1,5 @@ `include "VX_define.vh" +`include "dspba_library_ver.sv" module VX_fp_fpga ( input wire clk, @@ -25,68 +26,234 @@ module VX_fp_fpga ( input wire out_ready, output wire out_valid ); - wire fpnew_in_ready; - wire [`NUM_THREADS-1:0][31:0] fpnew_result; + localparam NUM_FPC = 12; + localparam FPC_BITS = `LOG2UP(NUM_FPC); + + reg [FPC_BITS-1:0] core_select; + + wire [NUM_FPC-1:0] core_in_ready; + wire [NUM_FPC-1:0][`NUM_THREADS-1:0][31:0] core_result; wire fpnew_has_fflags; wire [`NUM_THREADS-1:0][`FFG_BITS-1:0] fpnew_fflags; - wire [`ISTAG_BITS-1:0] fpnew_out_tag; - wire fpnew_out_ready; - wire fpnew_out_valid; + wire [NUM_FPC-1:0][`ISTAG_BITS-1:0] core_out_tag; + wire [NUM_FPC-1:0] core_out_ready; + wire [NUM_FPC-1:0] core_out_valid; - wire [`NUM_THREADS-1:0][31:0] add_result; - wire add_out_ready; - - VX_fpnew #( - .FMULADD (0), - .FDIVSQRT (0), - .FNONCOMP (1), - .FCONV (0) - ) fp_core ( - .clk (clk), - .reset (reset), - - .in_valid (in_valid), - .in_ready (fpnew_in_ready), - - .in_tag (in_tag), - - .op (op), - .frm (frm), - - .dataa (dataa), - .datab (datab), - .datac (datac), - .result (fpnew_result), - - .has_fflags (fpnew_has_fflags), - .fflags (fpnew_fflags), - - .out_tag (fpnew_out_tag), - - .out_ready (fpnew_out_ready), - .out_valid (fpnew_out_valid) - ); + reg negate_output; genvar i; - for (i = 0; i < `NUM_THREADS; i++) begin - acl_fp_add fp_add ( - .clock (clk), - .dataa (dataa), - .datab (datab), - .enable (add_out_ready), - .result (add_result[i]) - ); + + always @(*) begin + core_select = 0; + negate_output = 0; + case (op) + `FPU_ADD: core_select = 1; + `FPU_SUB: core_select = 2; + `FPU_MUL: core_select = 3; + `FPU_MADD: core_select = 4; + `FPU_MSUB: core_select = 5; + `FPU_NMSUB: begin core_select = 4; negate_output = 1; end + `FPU_NMADD: begin core_select = 5; negate_output = 1; end + `FPU_DIV: core_select = 6; + `FPU_SQRT: core_select = 7; + `FPU_CVTWS: core_select = 8; + `FPU_CVTWUS: core_select = 9; + `FPU_CVTSW: core_select = 10; + `FPU_CVTSWU: core_select = 11; + default:; + endcase end - assign in_reqady = fpnew_in_ready; - assign has_fflags = fpnew_has_fflags; - assign fflags = fpnew_fflags; - assign out_tag = fpnew_out_tag; - assign fpnew_out_ready = out_ready; + VX_fp_noncomp fp_noncomp ( + .clk (clk), + .reset (reset), + .in_valid (in_valid && (core_select == 0)), + .in_ready (core_in_ready[0]), + .in_tag (in_tag), + .op (op), + .frm (frm), + .dataa (dataa), + .datab (datab), + .result (core_result[0]), + .has_fflags (fpnew_has_fflags), + .fflags (fpnew_fflags), + .out_tag (core_out_tag[0]), + .out_ready (core_out_ready[0]), + .out_valid (core_out_valid[0]) + ); + + VX_fp_add fp_add ( + .clk (clk), + .reset (reset), + .in_valid (in_valid && (core_select == 1)), + .in_ready (core_in_ready[1]), + .in_tag (in_tag), + .dataa (dataa), + .datab (datab), + .result (core_result[1]), + .out_tag (core_out_tag[1]), + .out_ready (core_out_ready[1]), + .out_valid (core_out_valid[1]) + ); - assign add_out_ready = out_ready; + VX_fp_sub fp_sub ( + .clk (clk), + .reset (reset), + .in_valid (in_valid && (core_select == 2)), + .in_ready (core_in_ready[2]), + .in_tag (in_tag), + .dataa (dataa), + .datab (datab), + .result (core_result[2]), + .out_tag (core_out_tag[2]), + .out_ready (core_out_ready[2]), + .out_valid (core_out_valid[2]) + ); - assign result = fpnew_out_valid ? fpnew_result : add_result; - assign out_valid = fpnew_out_valid; + VX_fp_mul fp_mul ( + .clk (clk), + .reset (reset), + .in_valid (in_valid && (core_select == 3)), + .in_ready (core_in_ready[3]), + .in_tag (in_tag), + .dataa (dataa), + .datab (datab), + .result (core_result[3]), + .out_tag (core_out_tag[3]), + .out_ready (core_out_ready[3]), + .out_valid (core_out_valid[3]) + ); + + VX_fp_madd fp_madd ( + .clk (clk), + .reset (reset), + .in_valid (in_valid && (core_select == 4)), + .in_ready (core_in_ready[4]), + .in_tag (in_tag), + .negate (negate_output), + .dataa (dataa), + .datab (datab), + .datac (datac), + .result (core_result[4]), + .out_tag (core_out_tag[4]), + .out_ready (core_out_ready[4]), + .out_valid (core_out_valid[4]) + ); + + VX_fp_msub fp_msub ( + .clk (clk), + .reset (reset), + .in_valid (in_valid && (core_select == 5)), + .in_ready (core_in_ready[5]), + .in_tag (in_tag), + .negate (negate_output), + .dataa (dataa), + .datab (datab), + .datac (datac), + .result (core_result[5]), + .out_tag (core_out_tag[5]), + .out_ready (core_out_ready[5]), + .out_valid (core_out_valid[5]) + ); + + VX_fp_div fp_div ( + .clk (clk), + .reset (reset), + .in_valid (in_valid && (core_select == 6)), + .in_ready (core_in_ready[6]), + .in_tag (in_tag), + .dataa (dataa), + .datab (datab), + .result (core_result[6]), + .out_tag (core_out_tag[6]), + .out_ready (core_out_ready[6]), + .out_valid (core_out_valid[6]) + ); + + VX_fp_sqrt fp_sqrt ( + .clk (clk), + .reset (reset), + .in_valid (in_valid && (core_select == 7)), + .in_ready (core_in_ready[7]), + .in_tag (in_tag), + .dataa (dataa), + .result (core_result[7]), + .out_tag (core_out_tag[7]), + .out_ready (core_out_ready[7]), + .out_valid (core_out_valid[7]) + ); + + VX_fp_ftoi fp_ftoi ( + .clk (clk), + .reset (reset), + .in_valid (in_valid && (core_select == 8)), + .in_ready (core_in_ready[8]), + .in_tag (in_tag), + .dataa (dataa), + .result (core_result[8]), + .out_tag (core_out_tag[8]), + .out_ready (core_out_ready[8]), + .out_valid (core_out_valid[8]) + ); + + VX_fp_ftou fp_ftou ( + .clk (clk), + .reset (reset), + .in_valid (in_valid && (core_select == 9)), + .in_ready (core_in_ready[9]), + .in_tag (in_tag), + .dataa (dataa), + .result (core_result[9]), + .out_tag (core_out_tag[9]), + .out_ready (core_out_ready[9]), + .out_valid (core_out_valid[9]) + ); + + VX_fp_itof fp_itof ( + .clk (clk), + .reset (reset), + .in_valid (in_valid && (core_select == 10)), + .in_ready (core_in_ready[10]), + .in_tag (in_tag), + .dataa (dataa), + .result (core_result[10]), + .out_tag (core_out_tag[10]), + .out_ready (core_out_ready[10]), + .out_valid (core_out_valid[10]) + ); + + VX_fp_utof fp_utof ( + .clk (clk), + .reset (reset), + .in_valid (in_valid && (core_select == 11)), + .in_ready (core_in_ready[11]), + .in_tag (in_tag), + .dataa (dataa), + .result (core_result[11]), + .out_tag (core_out_tag[11]), + .out_ready (core_out_ready[11]), + .out_valid (core_out_valid[11]) + ); + + wire [FPC_BITS-1:0] fp_index; + wire fp_valid; + + VX_priority_encoder #( + .N(NUM_FPC) + ) wb_select ( + .data_in (core_out_valid), + .data_out (fp_index), + .valid_out (fp_valid) + ); + + for (i = 0; i < NUM_FPC; i++) begin + assign core_out_ready[i] = out_ready && (i == fp_index); + end + + assign has_fflags = fpnew_has_fflags && (fp_index == 0); + assign fflags = fpnew_fflags; + assign out_tag = core_out_tag[fp_index]; + assign result = core_result[fp_index]; + assign out_valid = fp_valid; endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/VX_fp_noncomp.v b/hw/rtl/fp_cores/VX_fp_noncomp.v new file mode 100644 index 00000000..b081e571 --- /dev/null +++ b/hw/rtl/fp_cores/VX_fp_noncomp.v @@ -0,0 +1,243 @@ +`include "VX_define.vh" + +module VX_fp_noncomp ( + input wire clk, + input wire reset, + + output wire in_ready, + input wire in_valid, + + input wire [`ISTAG_BITS-1:0] in_tag, + + input wire [`FPU_BITS-1:0] op, + input wire [`FRM_BITS-1:0] frm, + + input wire [`NUM_THREADS-1:0][31:0] dataa, + input wire [`NUM_THREADS-1:0][31:0] datab, + output wire [`NUM_THREADS-1:0][31:0] result, + + output wire has_fflags, + output wire [`NUM_THREADS-1:0][`FFG_BITS-1:0] fflags, + + output wire [`ISTAG_BITS-1:0] out_tag, + + input wire out_ready, + output wire out_valid +); + localparam NEG_INF = 32'h00000001, + NEG_NORM = 32'h00000002, + NEG_SUBNORM = 32'h00000004, + NEG_ZERO = 32'h00000008, + POS_ZERO = 32'h00000010, + POS_SUBNORM = 32'h00000020, + POS_NORM = 32'h00000040, + POS_INF = 32'h00000080, + SIG_NAN = 32'h00000100, + QUT_NAN = 32'h00000200; + + wire [`NUM_THREADS-1:0] a_sign, b_sign; + wire [`NUM_THREADS-1:0][7:0] a_exponent, b_exponent; + wire [`NUM_THREADS-1:0][22:0] a_mantissa, b_mantissa; + fp_type_t [`NUM_THREADS-1:0] a_type, b_type; + + wire [`NUM_THREADS-1:0] a_smaller, ab_equal; + + reg [`NUM_THREADS-1:0][31:0] fclass_mask; // generate a 10-bit mask for integer reg + reg [`NUM_THREADS-1:0][31:0] fminmax_res; // result of fmin/fmax + reg [`NUM_THREADS-1:0][31:0] fsgnj_res; // result of sign injection + reg [`NUM_THREADS-1:0][31:0] fcmp_res; // result of comparison + reg [`NUM_THREADS-1:0][ 4:0] fcmp_excp; // exception of comparison + + genvar i; + + // Setup + for (i = 0; i < `NUM_THREADS; i++) begin + assign a_sign[i] = dataa[i][31]; + assign a_exponent[i] = dataa[i][30:23]; + assign a_mantissa[i] = dataa[i][22:0]; + + assign b_sign[i] = datab[i][31]; + assign b_exponent[i] = datab[i][30:23]; + assign b_mantissa[i] = datab[i][22:0]; + + assign a_smaller[i] = (dataa[i] < datab[i]) ^ (a_sign[i] || b_sign[i]); + assign ab_equal[i] = (dataa[i] == datab[i]) | (a_type[i][4] & b_type[i][4]); + + VX_fp_type fp_type_a ( + .exponent(a_exponent[i]), + .mantissa(a_mantissa[i]), + .o_type(a_type[i]) + ); + + VX_fp_type fp_type_b ( + .exponent(b_exponent[i]), + .mantissa(b_mantissa[i]), + .o_type(b_type[i]) + ); + end + + // FCLASS + for (i = 0; i < `NUM_THREADS; i++) begin + always @(*) begin + if (a_type[i].is_normal) begin + fclass_mask[i] = a_sign[i] ? NEG_NORM : POS_NORM; + end + else if (a_type[i].is_inf) begin + fclass_mask[i] = a_sign[i] ? NEG_INF : POS_INF; + end + else if (a_type[i].is_zero) begin + fclass_mask[i] = a_sign[i] ? NEG_ZERO : POS_ZERO; + end + else if (a_type[i].is_subnormal) begin + fclass_mask[i] = a_sign[i] ? NEG_SUBNORM : POS_SUBNORM; + end + else if (a_type[i].is_nan) begin + fclass_mask[i] = {22'h0, a_type[i].is_quiet, a_type[i].is_signaling, 8'h0}; + end + else begin + fclass_mask[i] = QUT_NAN; + end + end + end + + // Min/Max + for (i = 0; i < `NUM_THREADS; i++) begin + always @(*) begin + if (a_type[i].is_nan && b_type[i].is_nan) + fminmax_res[i] = {1'b0, 8'hff, 1'b1, 22'd0}; // canonical qNaN + else if (a_type[i].is_nan) + fminmax_res[i] = datab[i]; + else if (b_type[i].is_nan) + fminmax_res[i] = dataa[i]; + else begin + case (op) // use LSB to distinguish MIN and MAX + `FPU_MIN: fminmax_res[i] = a_smaller[i] ? dataa[i] : datab[i]; + `FPU_MAX: fminmax_res[i] = a_smaller[i] ? datab[i] : dataa[i]; + default: fminmax_res[i] = 32'hdeadbeaf; // don't care value + endcase + end + end + end + + // Sign Injection + for (i = 0; i < `NUM_THREADS; i++) begin + always @(*) begin + case (op) + `FPU_SGNJ: fsgnj_res[i] = { b_sign[i], a_exponent[i], a_mantissa[i]}; + `FPU_SGNJN: fsgnj_res[i] = {~b_sign[i], a_exponent[i], a_mantissa[i]}; + `FPU_SGNJX: fsgnj_res[i] = { a_sign[i] ^ b_sign[i], a_exponent[i], a_mantissa[i]}; + default: fsgnj_res[i] = 32'hdeadbeaf; // don't care value + endcase + end + end + + // Comparison + for (i = 0; i < `NUM_THREADS; i++) begin + always @(*) begin + case (frm) + `FRM_RNE: begin + if (a_type[i].is_nan || b_type[i].is_nan) begin + fcmp_res[i] = 32'h0; // result is 0 when either operand is NaN + fcmp_excp[i] = {1'b1, 4'h0}; // raise NV flag when either operand is NaN + end + else begin + fcmp_res[i] = {31'h0, (a_smaller[i] | ab_equal[i])}; + fcmp_excp[i] = 5'h0; + end + end + `FRM_RTZ: begin + if (a_type[i].is_nan || b_type[i].is_nan) begin + fcmp_res[i] = 32'h0; // result is 0 when either operand is NaN + fcmp_excp[i] = {1'b1, 4'h0}; // raise NV flag when either operand is NaN + end + else begin + fcmp_res[i] = {31'h0, (a_smaller[i] & ~ab_equal[i])}; + fcmp_excp[i] = 5'h0; + end + end + `FRM_RDN: begin + if (a_type[i].is_nan || b_type[i].is_nan) begin + fcmp_res[i] = 32'h0; // result is 0 when either operand is NaN + // ** FEQS only raise NV flag when either operand is signaling NaN + fcmp_excp[i] = {(a_type[i].is_signaling | b_type[i].is_signaling), 4'h0}; + end + else begin + fcmp_res[i] = {31'h0, ab_equal[i]}; + fcmp_excp[i] = 5'h0; + end + end + default: begin + fcmp_res[i] = 32'hdeadbeaf; // don't care value + fcmp_excp[i] = 5'h0; + end + endcase + end + end + + // outputs + + reg tmp_valid; + reg tmp_has_fflags; + reg [`NUM_THREADS-1:0][`FFG_BITS-1:0] tmp_fflags; + reg [`NUM_THREADS-1:0][31:0] tmp_result; + + always @(*) begin + case (op) + `FPU_SGNJ: tmp_has_fflags = 0; + `FPU_SGNJN: tmp_has_fflags = 0; + `FPU_SGNJX: tmp_has_fflags = 0; + `FPU_MVXW: tmp_has_fflags = 0; + `FPU_MVWX: tmp_has_fflags = 0; + `FPU_CLASS: tmp_has_fflags = 0; + default: tmp_has_fflags = 1; + endcase + end + + for (i = 0; i < `NUM_THREADS; i++) begin + always @(*) begin + tmp_valid = 1'b1; + case (op) + `FPU_CLASS: begin + tmp_result[i] = fclass_mask[i]; + {tmp_fflags[i][`FFG_NV], tmp_fflags[i][`FFG_DZ], tmp_fflags[i][`FFG_OF], tmp_fflags[i][`FFG_UF], tmp_fflags[i][`FFG_NX]} = 5'h0; + end + `FPU_MVXW,`FPU_MVWX: begin + tmp_result[i] = dataa[i]; + {tmp_fflags[i][`FFG_NV], tmp_fflags[i][`FFG_DZ], tmp_fflags[i][`FFG_OF], tmp_fflags[i][`FFG_UF], tmp_fflags[i][`FFG_NX]} = 5'h0; + end + `FPU_MIN,`FPU_MAX: begin + tmp_result[i] = fminmax_res[i]; + {tmp_fflags[i][`FFG_NV], tmp_fflags[i][`FFG_DZ], tmp_fflags[i][`FFG_OF], tmp_fflags[i][`FFG_UF], tmp_fflags[i][`FFG_NX]} = {a_type[i][0] | b_type[i][0], 4'h0}; + end + `FPU_SGNJ,`FPU_SGNJN,`FPU_SGNJX: begin + tmp_result[i] = fsgnj_res[i]; + {tmp_fflags[i][`FFG_NV], tmp_fflags[i][`FFG_DZ], tmp_fflags[i][`FFG_OF], tmp_fflags[i][`FFG_UF], tmp_fflags[i][`FFG_NX]} = 5'h0; + end + `FPU_CMP: begin + tmp_result[i] = fcmp_res[i]; + {tmp_fflags[i][`FFG_NV], tmp_fflags[i][`FFG_DZ], tmp_fflags[i][`FFG_OF], tmp_fflags[i][`FFG_UF], tmp_fflags[i][`FFG_NX]} = fcmp_excp[i]; + end + default: begin + tmp_result[i] = 32'hdeadbeaf; + {tmp_fflags[i][`FFG_NV], tmp_fflags[i][`FFG_DZ], tmp_fflags[i][`FFG_OF], tmp_fflags[i][`FFG_UF], tmp_fflags[i][`FFG_NX]} = 5'h0; + tmp_valid = 1'b0; + end + endcase + end + end + + wire stall = ~out_ready && out_valid; + assign in_ready = ~stall; + + VX_generic_register #( + .N(1 + `ISTAG_BITS + (`NUM_THREADS * 32) + 1 + `FFG_BITS) + ) nc_reg ( + .clk (clk), + .reset (reset), + .stall (stall), + .flush (1'b0), + .in ({tmp_valid, in_tag, tmp_result, tmp_has_fflags, tmp_fflags}), + .out ({out_valid, out_tag, result, has_fflags, fflags}) + ); + +endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/VX_fp_type.v b/hw/rtl/fp_cores/VX_fp_type.v new file mode 100644 index 00000000..5e5aeb50 --- /dev/null +++ b/hw/rtl/fp_cores/VX_fp_type.v @@ -0,0 +1,19 @@ + +`include "VX_define.vh" + +module VX_fp_type ( + // inputs + input [7:0] exponent, + input [22:0] mantissa, + // outputs + output fp_type_t o_type +); + assign o_type.is_normal = (exponent != 8'd0) && (exponent != 8'hff); + assign o_type.is_zero = (exponent == 8'd0) && (mantissa == 23'd0); + assign o_type.is_subnormal = (exponent == 8'd0) && !o_type.is_zero; + assign o_type.is_inf = ((exponent == 8'hff) && (mantissa == 23'd0)); + assign o_type.is_nan = ((exponent == 8'hff) && (mantissa != 23'd0)); + assign o_type.is_signaling = o_type.is_nan && (mantissa[22] == 1'b0); + assign o_type.is_quiet = o_type.is_nan && !o_type.is_signaling; + +endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/VX_fpnew.v b/hw/rtl/fp_cores/VX_fpnew.v index 71ad066d..d56f8695 100644 --- a/hw/rtl/fp_cores/VX_fpnew.v +++ b/hw/rtl/fp_cores/VX_fpnew.v @@ -83,13 +83,13 @@ module VX_fpnew #( reg [FOP_BITS-1:0] fpu_op; reg [`FRM_BITS-1:0] fpu_rnd; reg fpu_op_mod; - reg fflags_en, fflags_en_o; + reg fpu_has_fflags, fpu_has_fflags_o; always @(*) begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = frm; fpu_op_mod = 0; - fflags_en = 1; + fpu_has_fflags = 1; fpu_operands[0] = dataa; fpu_operands[1] = datab; fpu_operands[2] = datac; @@ -112,18 +112,18 @@ module VX_fpnew #( `FPU_MSUB: begin fpu_op = fpnew_pkg::FMADD; fpu_op_mod = 1; end `FPU_NMSUB: begin fpu_op = fpnew_pkg::FNMSUB; end `FPU_NMADD: begin fpu_op = fpnew_pkg::FNMSUB; fpu_op_mod = 1; end - `FPU_SGNJ: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RNE; fflags_en = 0; end - `FPU_SGNJN: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RTZ; fflags_en = 0; end - `FPU_SGNJX: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RDN; fflags_en = 0; end + `FPU_SGNJ: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RNE; fpu_has_fflags = 0; end + `FPU_SGNJN: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RTZ; fpu_has_fflags = 0; end + `FPU_SGNJX: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RDN; fpu_has_fflags = 0; end `FPU_MIN: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `FRM_RNE; end `FPU_MAX: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `FRM_RTZ; end `FPU_CVTWS: begin fpu_op = fpnew_pkg::F2I; end `FPU_CVTWUS:begin fpu_op = fpnew_pkg::F2I; fpu_op_mod = 1; end `FPU_CVTSW: begin fpu_op = fpnew_pkg::I2F; end `FPU_CVTSWU:begin fpu_op = fpnew_pkg::I2F; fpu_op_mod = 1; end - `FPU_MVXW: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RUP; fflags_en = 0; end - `FPU_MVWX: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RUP; fflags_en = 0; end - `FPU_CLASS: begin fpu_op = fpnew_pkg::CLASSIFY; fflags_en = 0; end + `FPU_MVXW: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RUP; fpu_has_fflags = 0; end + `FPU_MVWX: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RUP; fpu_has_fflags = 0; end + `FPU_CLASS: begin fpu_op = fpnew_pkg::CLASSIFY; fpu_has_fflags = 0; end `FPU_CMP: begin fpu_op = fpnew_pkg::CMP; end default:; endcase @@ -150,13 +150,13 @@ module VX_fpnew #( .dst_fmt_i (fpnew_pkg::fp_format_e'(fpu_dst_fmt)), .int_fmt_i (fpnew_pkg::int_format_e'(fpu_int_fmt)), .vectorial_op_i (1'b0), - .tag_i ({fpu_in_tag, fflags_en, is_class_op_i}), + .tag_i ({fpu_in_tag, fpu_has_fflags, is_class_op_i}), .in_valid_i (fpu_in_valid), .in_ready_o (fpu_in_ready), .flush_i (reset), .result_o (fpu_result[0]), .status_o (fpu_status[0]), - .tag_o ({fpu_out_tag, fflags_en_o, is_class_op_o}), + .tag_o ({fpu_out_tag, fpu_has_fflags_o, is_class_op_o}), .out_valid_o (fpu_out_valid), .out_ready_i (fpu_out_ready), `UNUSED_PIN (busy_o) @@ -201,14 +201,14 @@ module VX_fpnew #( assign result = fpu_result; - assign has_fflags = fflags_en_o; + assign has_fflags = fpu_has_fflags_o; for (i = 0; i < `NUM_THREADS; i++) begin - assign fflags[i][0] = fpu_status[i].NX; - assign fflags[i][1] = fpu_status[i].UF; - assign fflags[i][2] = fpu_status[i].OF; - assign fflags[i][3] = fpu_status[i].DZ; - assign fflags[i][4] = fpu_status[i].NV; + assign fflags[i][`FFG_NX] = fpu_status[i].NX; + assign fflags[i][`FFG_UF] = fpu_status[i].UF; + assign fflags[i][`FFG_OF] = fpu_status[i].OF; + assign fflags[i][`FFG_DZ] = fpu_status[i].DZ; + assign fflags[i][`FFG_NV] = fpu_status[i].NV; end assign out_valid = fpu_out_valid; diff --git a/hw/rtl/fp_cores/altera/VX_fp_add.v b/hw/rtl/fp_cores/altera/VX_fp_add.v new file mode 100644 index 00000000..d06b80c2 --- /dev/null +++ b/hw/rtl/fp_cores/altera/VX_fp_add.v @@ -0,0 +1,80 @@ +`include "VX_define.vh" + +module VX_fp_add ( + input wire clk, + input wire reset, + + output wire in_ready, + input wire in_valid, + + input wire [`ISTAG_BITS-1:0] in_tag, + + input wire [`NUM_THREADS-1:0][31:0] dataa, + input wire [`NUM_THREADS-1:0][31:0] datab, + output wire [`NUM_THREADS-1:0][31:0] result, + + output wire [`ISTAG_BITS-1:0] out_tag, + + input wire out_ready, + output wire out_valid +); + wire stall = ~out_ready && out_valid; + wire enable = ~stall; + assign in_ready = enable; + + genvar i; + + for (i = 0; i < `NUM_THREADS; i++) begin + twentynm_fp_mac mac_fp_wys ( + // inputs + .accumulate(), + .chainin_overflow(), + .chainin_invalid(), + .chainin_underflow(), + .chainin_inexact(), + .ax(dataa[i]), + .ay(datab[i]), + .az(), + .clk({2'b00,clk}), + .ena({2'b11,enable}), + .aclr(2'b00), + .chainin(), + // outputs + .overflow(), + .invalid(), + .underflow(), + .inexact(), + .chainout_overflow(), + .chainout_invalid(), + .chainout_underflow(), + .chainout_inexact(), + .resulta(result[i]), + .chainout() + ); + defparam mac_fp_wys.operation_mode = "sp_add"; + defparam mac_fp_wys.use_chainin = "false"; + defparam mac_fp_wys.adder_subtract = "false"; + defparam mac_fp_wys.ax_clock = "0"; + defparam mac_fp_wys.ay_clock = "0"; + defparam mac_fp_wys.az_clock = "none"; + defparam mac_fp_wys.output_clock = "0"; + defparam mac_fp_wys.accumulate_clock = "none"; + defparam mac_fp_wys.ax_chainin_pl_clock = "none"; + defparam mac_fp_wys.accum_pipeline_clock = "none"; + defparam mac_fp_wys.mult_pipeline_clock = "none"; + defparam mac_fp_wys.adder_input_clock = "0"; + defparam mac_fp_wys.accum_adder_clock = "none"; + end + + VX_shift_register #( + .DATAW(`ISTAG_BITS + 1), + .DEPTH(1) + ) shift_reg ( + .clk(clk), + .reset(reset), + .enable(enable), + .in({in_tag, in_valid}), + .out({out_tag, out_valid}) + ); + +endmodule diff --git a/hw/rtl/fp_cores/altera/VX_fp_div.v b/hw/rtl/fp_cores/altera/VX_fp_div.v new file mode 100644 index 00000000..a08c1087 --- /dev/null +++ b/hw/rtl/fp_cores/altera/VX_fp_div.v @@ -0,0 +1,49 @@ +`include "VX_define.vh" + +module VX_fp_div ( + input wire clk, + input wire reset, + + output wire in_ready, + input wire in_valid, + + input wire [`ISTAG_BITS-1:0] in_tag, + + input wire [`NUM_THREADS-1:0][31:0] dataa, + input wire [`NUM_THREADS-1:0][31:0] datab, + output wire [`NUM_THREADS-1:0][31:0] result, + + output wire [`ISTAG_BITS-1:0] out_tag, + + input wire out_ready, + output wire out_valid +); + wire stall = ~out_ready && out_valid; + wire enable = ~stall; + assign in_ready = enable; + + genvar i; + + for (i = 0; i < `NUM_THREADS; i++) begin + acl_fp_div fdiv ( + .clk (clk), + .areset (1'b0), + .en (enable), + .a (dataa[i]), + .b (datab[i]), + .q (result[i]) + ); + end + + VX_shift_register #( + .DATAW(`ISTAG_BITS + 1), + .DEPTH(`LATENCY_FDIV) + ) shift_reg ( + .clk(clk), + .reset(reset), + .enable(enable), + .in({in_tag, in_valid}), + .out({out_tag, out_valid}) + ); + +endmodule diff --git a/hw/rtl/fp_cores/altera/VX_fp_ftoi.v b/hw/rtl/fp_cores/altera/VX_fp_ftoi.v new file mode 100644 index 00000000..b9e64db5 --- /dev/null +++ b/hw/rtl/fp_cores/altera/VX_fp_ftoi.v @@ -0,0 +1,47 @@ +`include "VX_define.vh" + +module VX_fp_ftoi ( + input wire clk, + input wire reset, + + output wire in_ready, + input wire in_valid, + + input wire [`ISTAG_BITS-1:0] in_tag, + + input wire [`NUM_THREADS-1:0][31:0] dataa, + output wire [`NUM_THREADS-1:0][31:0] result, + + output wire [`ISTAG_BITS-1:0] out_tag, + + input wire out_ready, + output wire out_valid +); + wire stall = ~out_ready && out_valid; + wire enable = ~stall; + assign in_ready = enable; + + genvar i; + + for (i = 0; i < `NUM_THREADS; i++) begin + acl_fp_ftoi ftoi ( + .clk (clk), + .areset (1'b0), + .en (enable), + .a (dataa[i]), + .q (result[i]) + ); + end + + VX_shift_register #( + .DATAW(`ISTAG_BITS + 1), + .DEPTH(`LATENCY_FTOI) + ) shift_reg ( + .clk(clk), + .reset(reset), + .enable(enable), + .in({in_tag, in_valid}), + .out({out_tag, out_valid}) + ); + +endmodule diff --git a/hw/rtl/fp_cores/altera/VX_fp_ftou.v b/hw/rtl/fp_cores/altera/VX_fp_ftou.v new file mode 100644 index 00000000..6044c2e5 --- /dev/null +++ b/hw/rtl/fp_cores/altera/VX_fp_ftou.v @@ -0,0 +1,47 @@ +`include "VX_define.vh" + +module VX_fp_ftou ( + input wire clk, + input wire reset, + + output wire in_ready, + input wire in_valid, + + input wire [`ISTAG_BITS-1:0] in_tag, + + input wire [`NUM_THREADS-1:0][31:0] dataa, + output wire [`NUM_THREADS-1:0][31:0] result, + + output wire [`ISTAG_BITS-1:0] out_tag, + + input wire out_ready, + output wire out_valid +); + wire stall = ~out_ready && out_valid; + wire enable = ~stall; + assign in_ready = enable; + + genvar i; + + for (i = 0; i < `NUM_THREADS; i++) begin + acl_fp_ftou ftou ( + .clk (clk), + .areset (1'b0), + .en (enable), + .a (dataa[i]), + .q (result[i]) + ); + end + + VX_shift_register #( + .DATAW(`ISTAG_BITS + 1), + .DEPTH(`LATENCY_FTOU) + ) shift_reg ( + .clk(clk), + .reset(reset), + .enable(enable), + .in({in_tag, in_valid}), + .out({out_tag, out_valid}) + ); + +endmodule diff --git a/hw/rtl/fp_cores/altera/VX_fp_itof.v b/hw/rtl/fp_cores/altera/VX_fp_itof.v new file mode 100644 index 00000000..4c8f3188 --- /dev/null +++ b/hw/rtl/fp_cores/altera/VX_fp_itof.v @@ -0,0 +1,47 @@ +`include "VX_define.vh" + +module VX_fp_itof ( + input wire clk, + input wire reset, + + output wire in_ready, + input wire in_valid, + + input wire [`ISTAG_BITS-1:0] in_tag, + + input wire [`NUM_THREADS-1:0][31:0] dataa, + output wire [`NUM_THREADS-1:0][31:0] result, + + output wire [`ISTAG_BITS-1:0] out_tag, + + input wire out_ready, + output wire out_valid +); + wire stall = ~out_ready && out_valid; + wire enable = ~stall; + assign in_ready = enable; + + genvar i; + + for (i = 0; i < `NUM_THREADS; i++) begin + acl_fp_itof itof ( + .clk (clk), + .areset (1'b0), + .en (enable), + .a (dataa[i]), + .q (result[i]) + ); + end + + VX_shift_register #( + .DATAW(`ISTAG_BITS + 1), + .DEPTH(`LATENCY_ITOF) + ) shift_reg ( + .clk(clk), + .reset(reset), + .enable(enable), + .in({in_tag, in_valid}), + .out({out_tag, out_valid}) + ); + +endmodule diff --git a/hw/rtl/fp_cores/altera/VX_fp_madd.v b/hw/rtl/fp_cores/altera/VX_fp_madd.v new file mode 100644 index 00000000..b6058e98 --- /dev/null +++ b/hw/rtl/fp_cores/altera/VX_fp_madd.v @@ -0,0 +1,145 @@ +`include "VX_define.vh" + +module VX_fp_madd ( + input wire clk, + input wire reset, + + output wire in_ready, + input wire in_valid, + + input wire [`ISTAG_BITS-1:0] in_tag, + + input wire [`NUM_THREADS-1:0][31:0] dataa, + input wire [`NUM_THREADS-1:0][31:0] datab, + input wire [`NUM_THREADS-1:0][31:0] datac, + output wire [`NUM_THREADS-1:0][31:0] result, + + input wire negate, + + output wire [`ISTAG_BITS-1:0] out_tag, + + input wire out_ready, + output wire out_valid +); + wire enable0, enable1; + assign in_ready = enable0 && enable1; + + wire [`NUM_THREADS-1:0][31:0] result_st0, result_st1; + wire [`ISTAG_BITS-1:0] out_tag_st0, out_tag_st1; + wire in_valid_st0, out_valid_st0, out_valid_st1; + + genvar i; + + for (i = 0; i < `NUM_THREADS; i++) begin + twentynm_fp_mac mac_fp_wys0 ( + // inputs + .accumulate(), + .chainin_overflow(), + .chainin_invalid(), + .chainin_underflow(), + .chainin_inexact(), + .ax(datac[i]), + .ay(datab[i]), + .az(dataa[i]), + .clk({2'b00,clk}), + .ena({2'b11,enable0}), + .aclr(2'b00), + .chainin(), + // outputs + .overflow(), + .invalid(), + .underflow(), + .inexact(), + .chainout_overflow(), + .chainout_invalid(), + .chainout_underflow(), + .chainout_inexact(), + .resulta(result_st0[i]), + .chainout() + ); + defparam mac_fp_wys0.operation_mode = "sp_mult_add"; + defparam mac_fp_wys0.use_chainin = "false"; + defparam mac_fp_wys0.adder_subtract = "false"; + defparam mac_fp_wys0.ax_clock = "0"; + defparam mac_fp_wys0.ay_clock = "0"; + defparam mac_fp_wys0.az_clock = "0"; + defparam mac_fp_wys0.output_clock = "0"; + defparam mac_fp_wys0.accumulate_clock = "none"; + defparam mac_fp_wys0.ax_chainin_pl_clock = "0"; + defparam mac_fp_wys0.accum_pipeline_clock = "none"; + defparam mac_fp_wys0.mult_pipeline_clock = "0"; + defparam mac_fp_wys0.adder_input_clock = "0"; + defparam mac_fp_wys0.accum_adder_clock = "none"; + + twentynm_fp_mac mac_fp_wys1 ( + // inputs + .accumulate(), + .chainin_overflow(), + .chainin_invalid(), + .chainin_underflow(), + .chainin_inexact(), + .ax(32'h0), + .ay(result_st0[i]), + .az(), + .clk({2'b00,clk}), + .ena({2'b11,enable1}), + .aclr(2'b00), + .chainin(), + // outputs + .overflow(), + .invalid(), + .underflow(), + .inexact(), + .chainout_overflow(), + .chainout_invalid(), + .chainout_underflow(), + .chainout_inexact(), + .resulta(result_st1[i]), + .chainout() + ); + defparam mac_fp_wys1.operation_mode = "sp_add"; + defparam mac_fp_wys1.use_chainin = "false"; + defparam mac_fp_wys1.adder_subtract = "true"; + defparam mac_fp_wys1.ax_clock = "0"; + defparam mac_fp_wys1.ay_clock = "0"; + defparam mac_fp_wys1.az_clock = "none"; + defparam mac_fp_wys1.output_clock = "0"; + defparam mac_fp_wys1.accumulate_clock = "none"; + defparam mac_fp_wys1.ax_chainin_pl_clock = "none"; + defparam mac_fp_wys1.accum_pipeline_clock = "none"; + defparam mac_fp_wys1.mult_pipeline_clock = "none"; + defparam mac_fp_wys1.adder_input_clock = "0"; + defparam mac_fp_wys1.accum_adder_clock = "none"; + end + + VX_shift_register #( + .DATAW(`ISTAG_BITS + 1 + 1), + .DEPTH(1) + ) shift_reg0 ( + .clk(clk), + .reset(reset), + .enable(enable0), + .in({in_tag, (in_valid && ~negate), (in_valid && negate)}), + .out({out_tag_st0, out_valid_st0, in_valid_st0}) + ); + + VX_shift_register #( + .DATAW(`ISTAG_BITS + 1), + .DEPTH(1) + ) shift_reg1 ( + .clk(clk), + .reset(reset), + .enable(enable1), + .in({in_tag_st0, in_valid_st0}), + .out({out_tag_st1, out_valid_st1}) + ); + + wire out_stall = ~out_ready && out_valid; + assign enable0 = ~out_stall; + assign enable1 = ~out_stall && ~(out_valid_st0 && out_valid_st1); // stall the negate stage if dual outputs + + assign result = out_valid_st0 ? result_st0 : result_st1; + assign out_tag = out_valid_st0 ? out_tag_st0 : out_tag_st1; + assign out_valid = out_valid_st0 || out_valid_st1; + +endmodule diff --git a/hw/rtl/fp_cores/altera/VX_fp_msub.v b/hw/rtl/fp_cores/altera/VX_fp_msub.v new file mode 100644 index 00000000..83a499d2 --- /dev/null +++ b/hw/rtl/fp_cores/altera/VX_fp_msub.v @@ -0,0 +1,145 @@ +`include "VX_define.vh" + +module VX_fp_msub ( + input wire clk, + input wire reset, + + output wire in_ready, + input wire in_valid, + + input wire [`ISTAG_BITS-1:0] in_tag, + + input wire [`NUM_THREADS-1:0][31:0] dataa, + input wire [`NUM_THREADS-1:0][31:0] datab, + input wire [`NUM_THREADS-1:0][31:0] datac, + output wire [`NUM_THREADS-1:0][31:0] result, + + input wire negate, + + output wire [`ISTAG_BITS-1:0] out_tag, + + input wire out_ready, + output wire out_valid +); + wire enable0, enable1; + assign in_ready = enable0 && enable1; + + wire [`NUM_THREADS-1:0][31:0] result_st0, result_st1; + wire [`ISTAG_BITS-1:0] out_tag_st0, out_tag_st1; + wire in_valid_st0, out_valid_st0, out_valid_st1; + + genvar i; + + for (i = 0; i < `NUM_THREADS; i++) begin + twentynm_fp_mac mac_fp_wys0 ( + // inputs + .accumulate(), + .chainin_overflow(), + .chainin_invalid(), + .chainin_underflow(), + .chainin_inexact(), + .ax(datac[i]), + .ay(datab[i]), + .az(dataa[i]), + .clk({2'b00,clk}), + .ena({2'b11,enable0}), + .aclr(2'b00), + .chainin(), + // outputs + .overflow(), + .invalid(), + .underflow(), + .inexact(), + .chainout_overflow(), + .chainout_invalid(), + .chainout_underflow(), + .chainout_inexact(), + .resulta(result_st0[i]), + .chainout() + ); + defparam mac_fp_wys0.operation_mode = "sp_mult_add"; + defparam mac_fp_wys0.use_chainin = "false"; + defparam mac_fp_wys0.adder_subtract = "true"; + defparam mac_fp_wys0.ax_clock = "0"; + defparam mac_fp_wys0.ay_clock = "0"; + defparam mac_fp_wys0.az_clock = "0"; + defparam mac_fp_wys0.output_clock = "0"; + defparam mac_fp_wys0.accumulate_clock = "none"; + defparam mac_fp_wys0.ax_chainin_pl_clock = "0"; + defparam mac_fp_wys0.accum_pipeline_clock = "none"; + defparam mac_fp_wys0.mult_pipeline_clock = "0"; + defparam mac_fp_wys0.adder_input_clock = "0"; + defparam mac_fp_wys0.accum_adder_clock = "none"; + + twentynm_fp_mac mac_fp_wys1 ( + // inputs + .accumulate(), + .chainin_overflow(), + .chainin_invalid(), + .chainin_underflow(), + .chainin_inexact(), + .ax(32'h0), + .ay(result_st0[i]), + .az(), + .clk({2'b00,clk}), + .ena({2'b11,enable1}), + .aclr(2'b00), + .chainin(), + // outputs + .overflow(), + .invalid(), + .underflow(), + .inexact(), + .chainout_overflow(), + .chainout_invalid(), + .chainout_underflow(), + .chainout_inexact(), + .resulta(result_st1[i]), + .chainout() + ); + defparam mac_fp_wys1.operation_mode = "sp_add"; + defparam mac_fp_wys1.use_chainin = "false"; + defparam mac_fp_wys1.adder_subtract = "true"; + defparam mac_fp_wys1.ax_clock = "0"; + defparam mac_fp_wys1.ay_clock = "0"; + defparam mac_fp_wys1.az_clock = "none"; + defparam mac_fp_wys1.output_clock = "0"; + defparam mac_fp_wys1.accumulate_clock = "none"; + defparam mac_fp_wys1.ax_chainin_pl_clock = "none"; + defparam mac_fp_wys1.accum_pipeline_clock = "none"; + defparam mac_fp_wys1.mult_pipeline_clock = "none"; + defparam mac_fp_wys1.adder_input_clock = "0"; + defparam mac_fp_wys1.accum_adder_clock = "none"; + end + + VX_shift_register #( + .DATAW(`ISTAG_BITS + 1 + 1), + .DEPTH(1) + ) shift_reg0 ( + .clk(clk), + .reset(reset), + .enable(enable0), + .in({in_tag, (in_valid && ~negate), (in_valid && negate)}), + .out({out_tag_st0, out_valid_st0, in_valid_st0}) + ); + + VX_shift_register #( + .DATAW(`ISTAG_BITS + 1), + .DEPTH(1) + ) shift_reg1 ( + .clk(clk), + .reset(reset), + .enable(enable1), + .in({in_tag_st0, in_valid_st0}), + .out({out_tag_st1, out_valid_st1}) + ); + + wire out_stall = ~out_ready && out_valid; + assign enable0 = ~out_stall; + assign enable1 = ~out_stall && ~(out_valid_st0 && out_valid_st1); // stall the negate stage if dual outputs + + assign result = out_valid_st0 ? result_st0 : result_st1; + assign out_tag = out_valid_st0 ? out_tag_st0 : out_tag_st1; + assign out_valid = out_valid_st0 || out_valid_st1; + +endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/altera/VX_fp_mul.v b/hw/rtl/fp_cores/altera/VX_fp_mul.v new file mode 100644 index 00000000..76709969 --- /dev/null +++ b/hw/rtl/fp_cores/altera/VX_fp_mul.v @@ -0,0 +1,80 @@ +`include "VX_define.vh" + +module VX_fp_mul ( + input wire clk, + input wire reset, + + output wire in_ready, + input wire in_valid, + + input wire [`ISTAG_BITS-1:0] in_tag, + + input wire [`NUM_THREADS-1:0][31:0] dataa, + input wire [`NUM_THREADS-1:0][31:0] datab, + output wire [`NUM_THREADS-1:0][31:0] result, + + output wire [`ISTAG_BITS-1:0] out_tag, + + input wire out_ready, + output wire out_valid +); + wire stall = ~out_ready && out_valid; + wire enable = ~stall; + assign in_ready = enable; + + genvar i; + + for (i = 0; i < `NUM_THREADS; i++) begin + twentynm_fp_mac mac_fp_wys ( + // inputs + .accumulate(), + .chainin_overflow(), + .chainin_invalid(), + .chainin_underflow(), + .chainin_inexact(), + .ax(), + .ay(datab[i]), + .az(dataa[i]), + .clk({2'b00,clk}), + .ena({2'b11,enable}), + .aclr(2'b00), + .chainin(), + // outputs + .overflow(), + .invalid(), + .underflow(), + .inexact(), + .chainout_overflow(), + .chainout_invalid(), + .chainout_underflow(), + .chainout_inexact(), + .resulta(result[i]), + .chainout() + ); + defparam mac_fp_wys.operation_mode = "sp_mult"; + defparam mac_fp_wys.use_chainin = "false"; + defparam mac_fp_wys.adder_subtract = "false"; + defparam mac_fp_wys.ax_clock = "none"; + defparam mac_fp_wys.ay_clock = "0"; + defparam mac_fp_wys.az_clock = "0"; + defparam mac_fp_wys.output_clock = "0"; + defparam mac_fp_wys.accumulate_clock = "none"; + defparam mac_fp_wys.ax_chainin_pl_clock = "none"; + defparam mac_fp_wys.accum_pipeline_clock = "none"; + defparam mac_fp_wys.mult_pipeline_clock = "0"; + defparam mac_fp_wys.adder_input_clock = "none"; + defparam mac_fp_wys.accum_adder_clock = "none"; + end + + VX_shift_register #( + .DATAW(`ISTAG_BITS + 1), + .DEPTH(1) + ) shift_reg ( + .clk(clk), + .reset(reset), + .enable(enable), + .in({in_tag, in_valid}), + .out({out_tag, out_valid}) + ); + +endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/altera/VX_fp_sqrt.v b/hw/rtl/fp_cores/altera/VX_fp_sqrt.v new file mode 100644 index 00000000..0a57adc7 --- /dev/null +++ b/hw/rtl/fp_cores/altera/VX_fp_sqrt.v @@ -0,0 +1,47 @@ +`include "VX_define.vh" + +module VX_fp_sqrt ( + input wire clk, + input wire reset, + + output wire in_ready, + input wire in_valid, + + input wire [`ISTAG_BITS-1:0] in_tag, + + input wire [`NUM_THREADS-1:0][31:0] dataa, + output wire [`NUM_THREADS-1:0][31:0] result, + + output wire [`ISTAG_BITS-1:0] out_tag, + + input wire out_ready, + output wire out_valid +); + wire stall = ~out_ready && out_valid; + wire enable = ~stall; + assign in_ready = enable; + + genvar i; + + for (i = 0; i < `NUM_THREADS; i++) begin + acl_fp_sqrt fsqrt ( + .clk (clk), + .areset (1'b0), + .en (enable), + .a (dataa[i]), + .q (result[i]) + ); + end + + VX_shift_register #( + .DATAW(`ISTAG_BITS + 1), + .DEPTH(`LATENCY_FSQRT) + ) shift_reg ( + .clk(clk), + .reset(reset), + .enable(enable), + .in({in_tag, in_valid}), + .out({out_tag, out_valid}) + ); + +endmodule diff --git a/hw/rtl/fp_cores/altera/VX_fp_sub.v b/hw/rtl/fp_cores/altera/VX_fp_sub.v new file mode 100644 index 00000000..986c7bf0 --- /dev/null +++ b/hw/rtl/fp_cores/altera/VX_fp_sub.v @@ -0,0 +1,80 @@ +`include "VX_define.vh" + +module VX_fp_sub ( + input wire clk, + input wire reset, + + output wire in_ready, + input wire in_valid, + + input wire [`ISTAG_BITS-1:0] in_tag, + + input wire [`NUM_THREADS-1:0][31:0] dataa, + input wire [`NUM_THREADS-1:0][31:0] datab, + output wire [`NUM_THREADS-1:0][31:0] result, + + output wire [`ISTAG_BITS-1:0] out_tag, + + input wire out_ready, + output wire out_valid +); + wire stall = ~out_ready && out_valid; + wire enable = ~stall; + assign in_ready = enable; + + genvar i; + + for (i = 0; i < `NUM_THREADS; i++) begin + twentynm_fp_mac mac_fp_wys ( + // inputs + .accumulate(), + .chainin_overflow(), + .chainin_invalid(), + .chainin_underflow(), + .chainin_inexact(), + .ax(dataa[i]), + .ay(datab[i]), + .az(), + .clk({2'b00,clk}), + .ena({2'b11,enable}), + .aclr(2'b00), + .chainin(), + // outputs + .overflow(), + .invalid(), + .underflow(), + .inexact(), + .chainout_overflow(), + .chainout_invalid(), + .chainout_underflow(), + .chainout_inexact(), + .resulta(result[i]), + .chainout() + ); + defparam mac_fp_wys.operation_mode = "sp_add"; + defparam mac_fp_wys.use_chainin = "false"; + defparam mac_fp_wys.adder_subtract = "true"; + defparam mac_fp_wys.ax_clock = "0"; + defparam mac_fp_wys.ay_clock = "0"; + defparam mac_fp_wys.az_clock = "none"; + defparam mac_fp_wys.output_clock = "0"; + defparam mac_fp_wys.accumulate_clock = "none"; + defparam mac_fp_wys.ax_chainin_pl_clock = "none"; + defparam mac_fp_wys.accum_pipeline_clock = "none"; + defparam mac_fp_wys.mult_pipeline_clock = "none"; + defparam mac_fp_wys.adder_input_clock = "0"; + defparam mac_fp_wys.accum_adder_clock = "none"; + end + + VX_shift_register #( + .DATAW(`ISTAG_BITS + 1), + .DEPTH(1) + ) shift_reg ( + .clk(clk), + .reset(reset), + .enable(enable), + .in({in_tag, in_valid}), + .out({out_tag, out_valid}) + ); + +endmodule diff --git a/hw/rtl/fp_cores/altera/VX_fp_utof.v b/hw/rtl/fp_cores/altera/VX_fp_utof.v new file mode 100644 index 00000000..e4169097 --- /dev/null +++ b/hw/rtl/fp_cores/altera/VX_fp_utof.v @@ -0,0 +1,47 @@ +`include "VX_define.vh" + +module VX_fp_utof ( + input wire clk, + input wire reset, + + output wire in_ready, + input wire in_valid, + + input wire [`ISTAG_BITS-1:0] in_tag, + + input wire [`NUM_THREADS-1:0][31:0] dataa, + output wire [`NUM_THREADS-1:0][31:0] result, + + output wire [`ISTAG_BITS-1:0] out_tag, + + input wire out_ready, + output wire out_valid +); + wire stall = ~out_ready && out_valid; + wire enable = ~stall; + assign in_ready = enable; + + genvar i; + + for (i = 0; i < `NUM_THREADS; i++) begin + acl_fp_utof utof ( + .clk (clk), + .areset (1'b0), + .en (enable), + .a (dataa[i]), + .q (result[i]) + ); + end + + VX_shift_register #( + .DATAW(`ISTAG_BITS + 1), + .DEPTH(`LATENCY_UTOF) + ) shift_reg ( + .clk(clk), + .reset(reset), + .enable(enable), + .in({in_tag, in_valid}), + .out({out_tag, out_valid}) + ); + +endmodule diff --git a/hw/rtl/fp_cores/altera/acl_fp_add.v b/hw/rtl/fp_cores/altera/acl_fp_add.v deleted file mode 100644 index 6024a22e..00000000 --- a/hw/rtl/fp_cores/altera/acl_fp_add.v +++ /dev/null @@ -1,67 +0,0 @@ -// (C) 1992-2016 Intel Corporation. -// Intel, the Intel logo, Intel, MegaCore, NIOS II, Quartus and TalkBack words -// and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. -// and/or other countries. Other marks and brands may be claimed as the property -// of others. See Trademarks on intel.com for full list of Intel trademarks or -// the Trademarks & Brands Names Database (if Intel) or See www.Intel.com/legal (if Altera) -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Intel MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - -module acl_fp_add(dataa, datab, clock, enable, result); - -input [31:0] dataa; -input [31:0] datab; -input clock, enable; - -output [31:0] result; - -// FP MAC wysiwyg -twentynm_fp_mac mac_fp_wys ( - // inputs - .accumulate(), - .chainin_overflow(), - .chainin_invalid(), - .chainin_underflow(), - .chainin_inexact(), - .ax(dataa), - .ay(datab), - .az(), - .clk({2'b00,clock}), - .ena({2'b11,enable}), - .aclr(2'b00), - .chainin(), - // outputs - .overflow(), - .invalid(), - .underflow(), - .inexact(), - .chainout_overflow(), - .chainout_invalid(), - .chainout_underflow(), - .chainout_inexact(), - .resulta(result), - .chainout() -); -defparam mac_fp_wys.operation_mode = "sp_add"; -defparam mac_fp_wys.use_chainin = "false"; -defparam mac_fp_wys.adder_subtract = "false"; -defparam mac_fp_wys.ax_clock = "0"; -defparam mac_fp_wys.ay_clock = "0"; -defparam mac_fp_wys.az_clock = "none"; -defparam mac_fp_wys.output_clock = "0"; -defparam mac_fp_wys.accumulate_clock = "none"; -defparam mac_fp_wys.ax_chainin_pl_clock = "none"; -defparam mac_fp_wys.accum_pipeline_clock = "none"; -defparam mac_fp_wys.mult_pipeline_clock = "none"; -defparam mac_fp_wys.adder_input_clock = "0"; -defparam mac_fp_wys.accum_adder_clock = "none"; - -endmodule diff --git a/hw/rtl/fp_cores/altera/acl_fp_div.sv b/hw/rtl/fp_cores/altera/acl_fp_div.sv new file mode 100644 index 00000000..ec08a90b --- /dev/null +++ b/hw/rtl/fp_cores/altera/acl_fp_div.sv @@ -0,0 +1,1605 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_fp_div +// SystemVerilog created on Wed Aug 5 12:58:14 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_fp_div ( + input wire [31:0] a, + input wire [31:0] b, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire [0:0] GND_q; + wire [0:0] VCC_q; + wire [7:0] cstBiasM1_uid6_fpDivTest_q; + wire [7:0] expX_uid9_fpDivTest_b; + wire [22:0] fracX_uid10_fpDivTest_b; + wire [0:0] signX_uid11_fpDivTest_b; + wire [7:0] expY_uid12_fpDivTest_b; + wire [22:0] fracY_uid13_fpDivTest_b; + wire [0:0] signY_uid14_fpDivTest_b; + wire [22:0] paddingY_uid15_fpDivTest_q; + wire [23:0] updatedY_uid16_fpDivTest_q; + wire [23:0] fracYZero_uid15_fpDivTest_a; + wire [0:0] fracYZero_uid15_fpDivTest_qi; + reg [0:0] fracYZero_uid15_fpDivTest_q; + wire [7:0] cstAllOWE_uid18_fpDivTest_q; + wire [7:0] cstAllZWE_uid20_fpDivTest_q; + wire [0:0] excZ_x_uid23_fpDivTest_qi; + reg [0:0] excZ_x_uid23_fpDivTest_q; + wire [0:0] expXIsMax_uid24_fpDivTest_qi; + reg [0:0] expXIsMax_uid24_fpDivTest_q; + wire [0:0] fracXIsZero_uid25_fpDivTest_qi; + reg [0:0] fracXIsZero_uid25_fpDivTest_q; + wire [0:0] fracXIsNotZero_uid26_fpDivTest_q; + wire [0:0] excI_x_uid27_fpDivTest_q; + wire [0:0] excN_x_uid28_fpDivTest_q; + wire [0:0] invExpXIsMax_uid29_fpDivTest_q; + wire [0:0] InvExpXIsZero_uid30_fpDivTest_q; + wire [0:0] excR_x_uid31_fpDivTest_q; + wire [0:0] excZ_y_uid37_fpDivTest_qi; + reg [0:0] excZ_y_uid37_fpDivTest_q; + wire [0:0] expXIsMax_uid38_fpDivTest_qi; + reg [0:0] expXIsMax_uid38_fpDivTest_q; + wire [0:0] fracXIsZero_uid39_fpDivTest_qi; + reg [0:0] fracXIsZero_uid39_fpDivTest_q; + wire [0:0] fracXIsNotZero_uid40_fpDivTest_q; + wire [0:0] excI_y_uid41_fpDivTest_q; + wire [0:0] excN_y_uid42_fpDivTest_q; + wire [0:0] invExpXIsMax_uid43_fpDivTest_q; + wire [0:0] InvExpXIsZero_uid44_fpDivTest_q; + wire [0:0] excR_y_uid45_fpDivTest_q; + wire [0:0] signR_uid46_fpDivTest_qi; + reg [0:0] signR_uid46_fpDivTest_q; + wire [8:0] expXmY_uid47_fpDivTest_a; + wire [8:0] expXmY_uid47_fpDivTest_b; + logic [8:0] expXmY_uid47_fpDivTest_o; + wire [8:0] expXmY_uid47_fpDivTest_q; + wire [10:0] expR_uid48_fpDivTest_a; + wire [10:0] expR_uid48_fpDivTest_b; + logic [10:0] expR_uid48_fpDivTest_o; + wire [9:0] expR_uid48_fpDivTest_q; + wire [8:0] yAddr_uid51_fpDivTest_b; + wire [13:0] yPE_uid52_fpDivTest_b; + wire [0:0] fracYPostZ_uid56_fpDivTest_qi; + reg [0:0] fracYPostZ_uid56_fpDivTest_q; + wire [23:0] lOAdded_uid58_fpDivTest_q; + wire [1:0] oFracXSE_bottomExtension_uid61_fpDivTest_q; + wire [25:0] oFracXSE_mergedSignalTM_uid63_fpDivTest_q; + wire [0:0] divValPreNormTrunc_uid66_fpDivTest_s; + reg [25:0] divValPreNormTrunc_uid66_fpDivTest_q; + wire [0:0] norm_uid67_fpDivTest_b; + wire [24:0] divValPreNormHigh_uid68_fpDivTest_in; + wire [23:0] divValPreNormHigh_uid68_fpDivTest_b; + wire [23:0] divValPreNormLow_uid69_fpDivTest_in; + wire [23:0] divValPreNormLow_uid69_fpDivTest_b; + wire [0:0] normFracRnd_uid70_fpDivTest_s; + reg [23:0] normFracRnd_uid70_fpDivTest_q; + wire [33:0] expFracRnd_uid71_fpDivTest_q; + wire [24:0] rndOp_uid75_fpDivTest_q; + wire [35:0] expFracPostRnd_uid76_fpDivTest_a; + wire [35:0] expFracPostRnd_uid76_fpDivTest_b; + logic [35:0] expFracPostRnd_uid76_fpDivTest_o; + wire [34:0] expFracPostRnd_uid76_fpDivTest_q; + wire [23:0] fracRPreExc_uid78_fpDivTest_in; + wire [22:0] fracRPreExc_uid78_fpDivTest_b; + wire [31:0] excRPreExc_uid79_fpDivTest_in; + wire [7:0] excRPreExc_uid79_fpDivTest_b; + wire [10:0] expRExt_uid80_fpDivTest_b; + wire [12:0] expUdf_uid81_fpDivTest_a; + wire [12:0] expUdf_uid81_fpDivTest_b; + logic [12:0] expUdf_uid81_fpDivTest_o; + wire [0:0] expUdf_uid81_fpDivTest_n; + wire [12:0] expOvf_uid84_fpDivTest_a; + wire [12:0] expOvf_uid84_fpDivTest_b; + logic [12:0] expOvf_uid84_fpDivTest_o; + wire [0:0] expOvf_uid84_fpDivTest_n; + wire [0:0] zeroOverReg_uid85_fpDivTest_q; + wire [0:0] regOverRegWithUf_uid86_fpDivTest_q; + wire [0:0] xRegOrZero_uid87_fpDivTest_q; + wire [0:0] regOrZeroOverInf_uid88_fpDivTest_q; + wire [0:0] excRZero_uid89_fpDivTest_qi; + reg [0:0] excRZero_uid89_fpDivTest_q; + wire [0:0] excXRYZ_uid90_fpDivTest_q; + wire [0:0] excXRYROvf_uid91_fpDivTest_q; + wire [0:0] excXIYZ_uid92_fpDivTest_q; + wire [0:0] excXIYR_uid93_fpDivTest_q; + wire [0:0] excRInf_uid94_fpDivTest_qi; + reg [0:0] excRInf_uid94_fpDivTest_q; + wire [0:0] excXZYZ_uid95_fpDivTest_q; + wire [0:0] excXIYI_uid96_fpDivTest_q; + wire [0:0] excRNaN_uid97_fpDivTest_qi; + reg [0:0] excRNaN_uid97_fpDivTest_q; + wire [2:0] concExc_uid98_fpDivTest_q; + reg [1:0] excREnc_uid99_fpDivTest_q; + wire [22:0] oneFracRPostExc2_uid100_fpDivTest_q; + wire [1:0] fracRPostExc_uid103_fpDivTest_s; + reg [22:0] fracRPostExc_uid103_fpDivTest_q; + wire [1:0] expRPostExc_uid107_fpDivTest_s; + reg [7:0] expRPostExc_uid107_fpDivTest_q; + wire [0:0] invExcRNaN_uid108_fpDivTest_q; + wire [0:0] sRPostExc_uid109_fpDivTest_q; + wire [31:0] divR_uid110_fpDivTest_q; + wire [11:0] yT1_uid124_invPolyEval_b; + wire [0:0] lowRangeB_uid126_invPolyEval_in; + wire [0:0] lowRangeB_uid126_invPolyEval_b; + wire [11:0] highBBits_uid127_invPolyEval_b; + wire [21:0] s1sumAHighB_uid128_invPolyEval_a; + wire [21:0] s1sumAHighB_uid128_invPolyEval_b; + logic [21:0] s1sumAHighB_uid128_invPolyEval_o; + wire [21:0] s1sumAHighB_uid128_invPolyEval_q; + wire [22:0] s1_uid129_invPolyEval_q; + wire [1:0] lowRangeB_uid132_invPolyEval_in; + wire [1:0] lowRangeB_uid132_invPolyEval_b; + wire [21:0] highBBits_uid133_invPolyEval_b; + wire [31:0] s2sumAHighB_uid134_invPolyEval_a; + wire [31:0] s2sumAHighB_uid134_invPolyEval_b; + logic [31:0] s2sumAHighB_uid134_invPolyEval_o; + wire [31:0] s2sumAHighB_uid134_invPolyEval_q; + wire [33:0] s2_uid135_invPolyEval_q; + wire [25:0] osig_uid138_prodDivPreNormProd_uid60_fpDivTest_b; + wire [12:0] osig_uid141_pT1_uid125_invPolyEval_b; + wire [23:0] osig_uid144_pT2_uid131_invPolyEval_b; + wire memoryC0_uid112_invTables_lutmem_reset0; + wire [30:0] memoryC0_uid112_invTables_lutmem_ia; + wire [8:0] memoryC0_uid112_invTables_lutmem_aa; + wire [8:0] memoryC0_uid112_invTables_lutmem_ab; + wire [30:0] memoryC0_uid112_invTables_lutmem_ir; + wire [30:0] memoryC0_uid112_invTables_lutmem_r; + wire memoryC1_uid115_invTables_lutmem_reset0; + wire [20:0] memoryC1_uid115_invTables_lutmem_ia; + wire [8:0] memoryC1_uid115_invTables_lutmem_aa; + wire [8:0] memoryC1_uid115_invTables_lutmem_ab; + wire [20:0] memoryC1_uid115_invTables_lutmem_ir; + wire [20:0] memoryC1_uid115_invTables_lutmem_r; + wire memoryC2_uid118_invTables_lutmem_reset0; + wire [11:0] memoryC2_uid118_invTables_lutmem_ia; + wire [8:0] memoryC2_uid118_invTables_lutmem_aa; + wire [8:0] memoryC2_uid118_invTables_lutmem_ab; + wire [11:0] memoryC2_uid118_invTables_lutmem_ir; + wire [11:0] memoryC2_uid118_invTables_lutmem_r; + wire prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_reset; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [25:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [25:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a1 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [23:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [23:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c1 [0:0]; + wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_p [0:0]; + wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_u [0:0]; + wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_w [0:0]; + wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_x [0:0]; + wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_y [0:0]; + reg [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_s [0:0]; + wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_qq; + wire [49:0] prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_q; + wire prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena0; + wire prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena1; + wire prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena2; + wire prodXY_uid140_pT1_uid125_invPolyEval_cma_reset; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [11:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_a0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [11:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_a1 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [11:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_c0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [11:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_c1 [0:0]; + wire signed [12:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_l [0:0]; + wire signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_p [0:0]; + wire signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_u [0:0]; + wire signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_w [0:0]; + wire signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_x [0:0]; + wire signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_y [0:0]; + reg signed [24:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_s [0:0]; + wire [23:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_qq; + wire [23:0] prodXY_uid140_pT1_uid125_invPolyEval_cma_q; + wire prodXY_uid140_pT1_uid125_invPolyEval_cma_ena0; + wire prodXY_uid140_pT1_uid125_invPolyEval_cma_ena1; + wire prodXY_uid140_pT1_uid125_invPolyEval_cma_ena2; + wire prodXY_uid143_pT2_uid131_invPolyEval_cma_reset; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [13:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_a0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [13:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_a1 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [22:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_c0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [22:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_c1 [0:0]; + wire signed [14:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_l [0:0]; + wire signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_p [0:0]; + wire signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_u [0:0]; + wire signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_w [0:0]; + wire signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_x [0:0]; + wire signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_y [0:0]; + reg signed [37:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_s [0:0]; + wire [36:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_qq; + wire [36:0] prodXY_uid143_pT2_uid131_invPolyEval_cma_q; + wire prodXY_uid143_pT2_uid131_invPolyEval_cma_ena0; + wire prodXY_uid143_pT2_uid131_invPolyEval_cma_ena1; + wire prodXY_uid143_pT2_uid131_invPolyEval_cma_ena2; + wire [31:0] invY_uid54_fpDivTest_merged_bit_select_in; + wire [25:0] invY_uid54_fpDivTest_merged_bit_select_b; + wire [0:0] invY_uid54_fpDivTest_merged_bit_select_c; + reg [25:0] redist0_invY_uid54_fpDivTest_merged_bit_select_b_1_q; + reg [0:0] redist1_lowRangeB_uid126_invPolyEval_b_1_q; + reg [7:0] redist2_excRPreExc_uid79_fpDivTest_b_1_q; + reg [22:0] redist3_fracRPreExc_uid78_fpDivTest_b_1_q; + reg [0:0] redist4_norm_uid67_fpDivTest_b_1_q; + reg [23:0] redist5_lOAdded_uid58_fpDivTest_q_3_q; + reg [0:0] redist6_fracYPostZ_uid56_fpDivTest_q_4_q; + reg [13:0] redist7_yPE_uid52_fpDivTest_b_2_q; + reg [8:0] redist9_yAddr_uid51_fpDivTest_b_3_q; + reg [8:0] redist10_yAddr_uid51_fpDivTest_b_7_q; + reg [0:0] redist12_signR_uid46_fpDivTest_q_16_q; + reg [0:0] redist13_fracXIsZero_uid39_fpDivTest_q_15_q; + reg [0:0] redist14_expXIsMax_uid38_fpDivTest_q_15_q; + reg [0:0] redist15_excZ_y_uid37_fpDivTest_q_15_q; + reg [0:0] redist16_fracXIsZero_uid25_fpDivTest_q_5_q; + reg [0:0] redist17_expXIsMax_uid24_fpDivTest_q_15_q; + reg [0:0] redist18_excZ_x_uid23_fpDivTest_q_15_q; + reg [0:0] redist19_fracYZero_uid15_fpDivTest_q_9_q; + wire redist8_yPE_uid52_fpDivTest_b_6_mem_reset0; + wire [13:0] redist8_yPE_uid52_fpDivTest_b_6_mem_ia; + wire [1:0] redist8_yPE_uid52_fpDivTest_b_6_mem_aa; + wire [1:0] redist8_yPE_uid52_fpDivTest_b_6_mem_ab; + wire [13:0] redist8_yPE_uid52_fpDivTest_b_6_mem_iq; + wire [13:0] redist8_yPE_uid52_fpDivTest_b_6_mem_q; + wire [1:0] redist8_yPE_uid52_fpDivTest_b_6_rdcnt_q; + (* preserve *) reg [1:0] redist8_yPE_uid52_fpDivTest_b_6_rdcnt_i; + (* preserve *) reg redist8_yPE_uid52_fpDivTest_b_6_rdcnt_eq; + wire [0:0] redist8_yPE_uid52_fpDivTest_b_6_rdmux_s; + reg [1:0] redist8_yPE_uid52_fpDivTest_b_6_rdmux_q; + reg [1:0] redist8_yPE_uid52_fpDivTest_b_6_wraddr_q; + wire [1:0] redist8_yPE_uid52_fpDivTest_b_6_mem_last_q; + wire [0:0] redist8_yPE_uid52_fpDivTest_b_6_cmp_q; + reg [0:0] redist8_yPE_uid52_fpDivTest_b_6_cmpReg_q; + wire [0:0] redist8_yPE_uid52_fpDivTest_b_6_notEnable_q; + wire [0:0] redist8_yPE_uid52_fpDivTest_b_6_nor_q; + (* preserve_syn_only *) reg [0:0] redist8_yPE_uid52_fpDivTest_b_6_sticky_ena_q; + wire [0:0] redist8_yPE_uid52_fpDivTest_b_6_enaAnd_q; + reg [8:0] redist11_expXmY_uid47_fpDivTest_q_13_outputreg_q; + wire redist11_expXmY_uid47_fpDivTest_q_13_mem_reset0; + wire [8:0] redist11_expXmY_uid47_fpDivTest_q_13_mem_ia; + wire [3:0] redist11_expXmY_uid47_fpDivTest_q_13_mem_aa; + wire [3:0] redist11_expXmY_uid47_fpDivTest_q_13_mem_ab; + wire [8:0] redist11_expXmY_uid47_fpDivTest_q_13_mem_iq; + wire [8:0] redist11_expXmY_uid47_fpDivTest_q_13_mem_q; + wire [3:0] redist11_expXmY_uid47_fpDivTest_q_13_rdcnt_q; + (* preserve *) reg [3:0] redist11_expXmY_uid47_fpDivTest_q_13_rdcnt_i; + (* preserve *) reg redist11_expXmY_uid47_fpDivTest_q_13_rdcnt_eq; + wire [0:0] redist11_expXmY_uid47_fpDivTest_q_13_rdmux_s; + reg [3:0] redist11_expXmY_uid47_fpDivTest_q_13_rdmux_q; + reg [3:0] redist11_expXmY_uid47_fpDivTest_q_13_wraddr_q; + wire [4:0] redist11_expXmY_uid47_fpDivTest_q_13_mem_last_q; + wire [4:0] redist11_expXmY_uid47_fpDivTest_q_13_cmp_b; + wire [0:0] redist11_expXmY_uid47_fpDivTest_q_13_cmp_q; + reg [0:0] redist11_expXmY_uid47_fpDivTest_q_13_cmpReg_q; + wire [0:0] redist11_expXmY_uid47_fpDivTest_q_13_notEnable_q; + wire [0:0] redist11_expXmY_uid47_fpDivTest_q_13_nor_q; + (* preserve_syn_only *) reg [0:0] redist11_expXmY_uid47_fpDivTest_q_13_sticky_ena_q; + wire [0:0] redist11_expXmY_uid47_fpDivTest_q_13_enaAnd_q; + reg [22:0] redist20_fracX_uid10_fpDivTest_b_10_outputreg_q; + wire redist20_fracX_uid10_fpDivTest_b_10_mem_reset0; + wire [22:0] redist20_fracX_uid10_fpDivTest_b_10_mem_ia; + wire [2:0] redist20_fracX_uid10_fpDivTest_b_10_mem_aa; + wire [2:0] redist20_fracX_uid10_fpDivTest_b_10_mem_ab; + wire [22:0] redist20_fracX_uid10_fpDivTest_b_10_mem_iq; + wire [22:0] redist20_fracX_uid10_fpDivTest_b_10_mem_q; + wire [2:0] redist20_fracX_uid10_fpDivTest_b_10_rdcnt_q; + (* preserve *) reg [2:0] redist20_fracX_uid10_fpDivTest_b_10_rdcnt_i; + wire [0:0] redist20_fracX_uid10_fpDivTest_b_10_rdmux_s; + reg [2:0] redist20_fracX_uid10_fpDivTest_b_10_rdmux_q; + reg [2:0] redist20_fracX_uid10_fpDivTest_b_10_wraddr_q; + wire [3:0] redist20_fracX_uid10_fpDivTest_b_10_mem_last_q; + wire [3:0] redist20_fracX_uid10_fpDivTest_b_10_cmp_b; + wire [0:0] redist20_fracX_uid10_fpDivTest_b_10_cmp_q; + reg [0:0] redist20_fracX_uid10_fpDivTest_b_10_cmpReg_q; + wire [0:0] redist20_fracX_uid10_fpDivTest_b_10_notEnable_q; + wire [0:0] redist20_fracX_uid10_fpDivTest_b_10_nor_q; + (* preserve_syn_only *) reg [0:0] redist20_fracX_uid10_fpDivTest_b_10_sticky_ena_q; + wire [0:0] redist20_fracX_uid10_fpDivTest_b_10_enaAnd_q; + + + // fracY_uid13_fpDivTest(BITSELECT,12)@0 + assign fracY_uid13_fpDivTest_b = b[22:0]; + + // paddingY_uid15_fpDivTest(CONSTANT,14) + assign paddingY_uid15_fpDivTest_q = 23'b00000000000000000000000; + + // fracXIsZero_uid39_fpDivTest(LOGICAL,38)@0 + 1 + assign fracXIsZero_uid39_fpDivTest_qi = paddingY_uid15_fpDivTest_q == fracY_uid13_fpDivTest_b ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + fracXIsZero_uid39_fpDivTest_delay ( .xin(fracXIsZero_uid39_fpDivTest_qi), .xout(fracXIsZero_uid39_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist13_fracXIsZero_uid39_fpDivTest_q_15(DELAY,165) + dspba_delay_ver #( .width(1), .depth(14), .reset_kind("ASYNC") ) + redist13_fracXIsZero_uid39_fpDivTest_q_15 ( .xin(fracXIsZero_uid39_fpDivTest_q), .xout(redist13_fracXIsZero_uid39_fpDivTest_q_15_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // cstAllOWE_uid18_fpDivTest(CONSTANT,17) + assign cstAllOWE_uid18_fpDivTest_q = 8'b11111111; + + // expY_uid12_fpDivTest(BITSELECT,11)@0 + assign expY_uid12_fpDivTest_b = b[30:23]; + + // expXIsMax_uid38_fpDivTest(LOGICAL,37)@0 + 1 + assign expXIsMax_uid38_fpDivTest_qi = expY_uid12_fpDivTest_b == cstAllOWE_uid18_fpDivTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + expXIsMax_uid38_fpDivTest_delay ( .xin(expXIsMax_uid38_fpDivTest_qi), .xout(expXIsMax_uid38_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist14_expXIsMax_uid38_fpDivTest_q_15(DELAY,166) + dspba_delay_ver #( .width(1), .depth(14), .reset_kind("ASYNC") ) + redist14_expXIsMax_uid38_fpDivTest_q_15 ( .xin(expXIsMax_uid38_fpDivTest_q), .xout(redist14_expXIsMax_uid38_fpDivTest_q_15_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excI_y_uid41_fpDivTest(LOGICAL,40)@15 + assign excI_y_uid41_fpDivTest_q = redist14_expXIsMax_uid38_fpDivTest_q_15_q & redist13_fracXIsZero_uid39_fpDivTest_q_15_q; + + // redist20_fracX_uid10_fpDivTest_b_10_notEnable(LOGICAL,204) + assign redist20_fracX_uid10_fpDivTest_b_10_notEnable_q = ~ (en); + + // redist20_fracX_uid10_fpDivTest_b_10_nor(LOGICAL,205) + assign redist20_fracX_uid10_fpDivTest_b_10_nor_q = ~ (redist20_fracX_uid10_fpDivTest_b_10_notEnable_q | redist20_fracX_uid10_fpDivTest_b_10_sticky_ena_q); + + // redist20_fracX_uid10_fpDivTest_b_10_mem_last(CONSTANT,201) + assign redist20_fracX_uid10_fpDivTest_b_10_mem_last_q = 4'b0110; + + // redist20_fracX_uid10_fpDivTest_b_10_cmp(LOGICAL,202) + assign redist20_fracX_uid10_fpDivTest_b_10_cmp_b = {1'b0, redist20_fracX_uid10_fpDivTest_b_10_rdmux_q}; + assign redist20_fracX_uid10_fpDivTest_b_10_cmp_q = redist20_fracX_uid10_fpDivTest_b_10_mem_last_q == redist20_fracX_uid10_fpDivTest_b_10_cmp_b ? 1'b1 : 1'b0; + + // redist20_fracX_uid10_fpDivTest_b_10_cmpReg(REG,203) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist20_fracX_uid10_fpDivTest_b_10_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist20_fracX_uid10_fpDivTest_b_10_cmpReg_q <= redist20_fracX_uid10_fpDivTest_b_10_cmp_q; + end + end + + // redist20_fracX_uid10_fpDivTest_b_10_sticky_ena(REG,206) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist20_fracX_uid10_fpDivTest_b_10_sticky_ena_q <= 1'b0; + end + else if (redist20_fracX_uid10_fpDivTest_b_10_nor_q == 1'b1) + begin + redist20_fracX_uid10_fpDivTest_b_10_sticky_ena_q <= redist20_fracX_uid10_fpDivTest_b_10_cmpReg_q; + end + end + + // redist20_fracX_uid10_fpDivTest_b_10_enaAnd(LOGICAL,207) + assign redist20_fracX_uid10_fpDivTest_b_10_enaAnd_q = redist20_fracX_uid10_fpDivTest_b_10_sticky_ena_q & en; + + // redist20_fracX_uid10_fpDivTest_b_10_rdcnt(COUNTER,198) + // low=0, high=7, step=1, init=0 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist20_fracX_uid10_fpDivTest_b_10_rdcnt_i <= 3'd0; + end + else if (en == 1'b1) + begin + redist20_fracX_uid10_fpDivTest_b_10_rdcnt_i <= $unsigned(redist20_fracX_uid10_fpDivTest_b_10_rdcnt_i) + $unsigned(3'd1); + end + end + assign redist20_fracX_uid10_fpDivTest_b_10_rdcnt_q = redist20_fracX_uid10_fpDivTest_b_10_rdcnt_i[2:0]; + + // redist20_fracX_uid10_fpDivTest_b_10_rdmux(MUX,199) + assign redist20_fracX_uid10_fpDivTest_b_10_rdmux_s = en; + always @(redist20_fracX_uid10_fpDivTest_b_10_rdmux_s or redist20_fracX_uid10_fpDivTest_b_10_wraddr_q or redist20_fracX_uid10_fpDivTest_b_10_rdcnt_q) + begin + unique case (redist20_fracX_uid10_fpDivTest_b_10_rdmux_s) + 1'b0 : redist20_fracX_uid10_fpDivTest_b_10_rdmux_q = redist20_fracX_uid10_fpDivTest_b_10_wraddr_q; + 1'b1 : redist20_fracX_uid10_fpDivTest_b_10_rdmux_q = redist20_fracX_uid10_fpDivTest_b_10_rdcnt_q; + default : redist20_fracX_uid10_fpDivTest_b_10_rdmux_q = 3'b0; + endcase + end + + // VCC(CONSTANT,1) + assign VCC_q = 1'b1; + + // fracX_uid10_fpDivTest(BITSELECT,9)@0 + assign fracX_uid10_fpDivTest_b = a[22:0]; + + // redist20_fracX_uid10_fpDivTest_b_10_wraddr(REG,200) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist20_fracX_uid10_fpDivTest_b_10_wraddr_q <= 3'b111; + end + else + begin + redist20_fracX_uid10_fpDivTest_b_10_wraddr_q <= redist20_fracX_uid10_fpDivTest_b_10_rdmux_q; + end + end + + // redist20_fracX_uid10_fpDivTest_b_10_mem(DUALMEM,197) + assign redist20_fracX_uid10_fpDivTest_b_10_mem_ia = fracX_uid10_fpDivTest_b; + assign redist20_fracX_uid10_fpDivTest_b_10_mem_aa = redist20_fracX_uid10_fpDivTest_b_10_wraddr_q; + assign redist20_fracX_uid10_fpDivTest_b_10_mem_ab = redist20_fracX_uid10_fpDivTest_b_10_rdmux_q; + assign redist20_fracX_uid10_fpDivTest_b_10_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(23), + .widthad_a(3), + .numwords_a(8), + .width_b(23), + .widthad_b(3), + .numwords_b(8), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_aclr_b("CLEAR1"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Arria 10") + ) redist20_fracX_uid10_fpDivTest_b_10_mem_dmem ( + .clocken1(redist20_fracX_uid10_fpDivTest_b_10_enaAnd_q[0]), + .clocken0(VCC_q[0]), + .clock0(clk), + .aclr1(redist20_fracX_uid10_fpDivTest_b_10_mem_reset0), + .clock1(clk), + .address_a(redist20_fracX_uid10_fpDivTest_b_10_mem_aa), + .data_a(redist20_fracX_uid10_fpDivTest_b_10_mem_ia), + .wren_a(en[0]), + .address_b(redist20_fracX_uid10_fpDivTest_b_10_mem_ab), + .q_b(redist20_fracX_uid10_fpDivTest_b_10_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist20_fracX_uid10_fpDivTest_b_10_mem_q = redist20_fracX_uid10_fpDivTest_b_10_mem_iq[22:0]; + + // redist20_fracX_uid10_fpDivTest_b_10_outputreg(DELAY,196) + dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) + redist20_fracX_uid10_fpDivTest_b_10_outputreg ( .xin(redist20_fracX_uid10_fpDivTest_b_10_mem_q), .xout(redist20_fracX_uid10_fpDivTest_b_10_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // fracXIsZero_uid25_fpDivTest(LOGICAL,24)@10 + 1 + assign fracXIsZero_uid25_fpDivTest_qi = paddingY_uid15_fpDivTest_q == redist20_fracX_uid10_fpDivTest_b_10_outputreg_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + fracXIsZero_uid25_fpDivTest_delay ( .xin(fracXIsZero_uid25_fpDivTest_qi), .xout(fracXIsZero_uid25_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist16_fracXIsZero_uid25_fpDivTest_q_5(DELAY,168) + dspba_delay_ver #( .width(1), .depth(4), .reset_kind("ASYNC") ) + redist16_fracXIsZero_uid25_fpDivTest_q_5 ( .xin(fracXIsZero_uid25_fpDivTest_q), .xout(redist16_fracXIsZero_uid25_fpDivTest_q_5_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expX_uid9_fpDivTest(BITSELECT,8)@0 + assign expX_uid9_fpDivTest_b = a[30:23]; + + // expXIsMax_uid24_fpDivTest(LOGICAL,23)@0 + 1 + assign expXIsMax_uid24_fpDivTest_qi = expX_uid9_fpDivTest_b == cstAllOWE_uid18_fpDivTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + expXIsMax_uid24_fpDivTest_delay ( .xin(expXIsMax_uid24_fpDivTest_qi), .xout(expXIsMax_uid24_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist17_expXIsMax_uid24_fpDivTest_q_15(DELAY,169) + dspba_delay_ver #( .width(1), .depth(14), .reset_kind("ASYNC") ) + redist17_expXIsMax_uid24_fpDivTest_q_15 ( .xin(expXIsMax_uid24_fpDivTest_q), .xout(redist17_expXIsMax_uid24_fpDivTest_q_15_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excI_x_uid27_fpDivTest(LOGICAL,26)@15 + assign excI_x_uid27_fpDivTest_q = redist17_expXIsMax_uid24_fpDivTest_q_15_q & redist16_fracXIsZero_uid25_fpDivTest_q_5_q; + + // excXIYI_uid96_fpDivTest(LOGICAL,95)@15 + assign excXIYI_uid96_fpDivTest_q = excI_x_uid27_fpDivTest_q & excI_y_uid41_fpDivTest_q; + + // fracXIsNotZero_uid40_fpDivTest(LOGICAL,39)@15 + assign fracXIsNotZero_uid40_fpDivTest_q = ~ (redist13_fracXIsZero_uid39_fpDivTest_q_15_q); + + // excN_y_uid42_fpDivTest(LOGICAL,41)@15 + assign excN_y_uid42_fpDivTest_q = redist14_expXIsMax_uid38_fpDivTest_q_15_q & fracXIsNotZero_uid40_fpDivTest_q; + + // fracXIsNotZero_uid26_fpDivTest(LOGICAL,25)@15 + assign fracXIsNotZero_uid26_fpDivTest_q = ~ (redist16_fracXIsZero_uid25_fpDivTest_q_5_q); + + // excN_x_uid28_fpDivTest(LOGICAL,27)@15 + assign excN_x_uid28_fpDivTest_q = redist17_expXIsMax_uid24_fpDivTest_q_15_q & fracXIsNotZero_uid26_fpDivTest_q; + + // cstAllZWE_uid20_fpDivTest(CONSTANT,19) + assign cstAllZWE_uid20_fpDivTest_q = 8'b00000000; + + // excZ_y_uid37_fpDivTest(LOGICAL,36)@0 + 1 + assign excZ_y_uid37_fpDivTest_qi = expY_uid12_fpDivTest_b == cstAllZWE_uid20_fpDivTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + excZ_y_uid37_fpDivTest_delay ( .xin(excZ_y_uid37_fpDivTest_qi), .xout(excZ_y_uid37_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist15_excZ_y_uid37_fpDivTest_q_15(DELAY,167) + dspba_delay_ver #( .width(1), .depth(14), .reset_kind("ASYNC") ) + redist15_excZ_y_uid37_fpDivTest_q_15 ( .xin(excZ_y_uid37_fpDivTest_q), .xout(redist15_excZ_y_uid37_fpDivTest_q_15_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excZ_x_uid23_fpDivTest(LOGICAL,22)@0 + 1 + assign excZ_x_uid23_fpDivTest_qi = expX_uid9_fpDivTest_b == cstAllZWE_uid20_fpDivTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + excZ_x_uid23_fpDivTest_delay ( .xin(excZ_x_uid23_fpDivTest_qi), .xout(excZ_x_uid23_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist18_excZ_x_uid23_fpDivTest_q_15(DELAY,170) + dspba_delay_ver #( .width(1), .depth(14), .reset_kind("ASYNC") ) + redist18_excZ_x_uid23_fpDivTest_q_15 ( .xin(excZ_x_uid23_fpDivTest_q), .xout(redist18_excZ_x_uid23_fpDivTest_q_15_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excXZYZ_uid95_fpDivTest(LOGICAL,94)@15 + assign excXZYZ_uid95_fpDivTest_q = redist18_excZ_x_uid23_fpDivTest_q_15_q & redist15_excZ_y_uid37_fpDivTest_q_15_q; + + // excRNaN_uid97_fpDivTest(LOGICAL,96)@15 + 1 + assign excRNaN_uid97_fpDivTest_qi = excXZYZ_uid95_fpDivTest_q | excN_x_uid28_fpDivTest_q | excN_y_uid42_fpDivTest_q | excXIYI_uid96_fpDivTest_q; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + excRNaN_uid97_fpDivTest_delay ( .xin(excRNaN_uid97_fpDivTest_qi), .xout(excRNaN_uid97_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // invExcRNaN_uid108_fpDivTest(LOGICAL,107)@16 + assign invExcRNaN_uid108_fpDivTest_q = ~ (excRNaN_uid97_fpDivTest_q); + + // signY_uid14_fpDivTest(BITSELECT,13)@0 + assign signY_uid14_fpDivTest_b = b[31:31]; + + // signX_uid11_fpDivTest(BITSELECT,10)@0 + assign signX_uid11_fpDivTest_b = a[31:31]; + + // signR_uid46_fpDivTest(LOGICAL,45)@0 + 1 + assign signR_uid46_fpDivTest_qi = signX_uid11_fpDivTest_b ^ signY_uid14_fpDivTest_b; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + signR_uid46_fpDivTest_delay ( .xin(signR_uid46_fpDivTest_qi), .xout(signR_uid46_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist12_signR_uid46_fpDivTest_q_16(DELAY,164) + dspba_delay_ver #( .width(1), .depth(15), .reset_kind("ASYNC") ) + redist12_signR_uid46_fpDivTest_q_16 ( .xin(signR_uid46_fpDivTest_q), .xout(redist12_signR_uid46_fpDivTest_q_16_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // sRPostExc_uid109_fpDivTest(LOGICAL,108)@16 + assign sRPostExc_uid109_fpDivTest_q = redist12_signR_uid46_fpDivTest_q_16_q & invExcRNaN_uid108_fpDivTest_q; + + // lOAdded_uid58_fpDivTest(BITJOIN,57)@10 + assign lOAdded_uid58_fpDivTest_q = {VCC_q, redist20_fracX_uid10_fpDivTest_b_10_outputreg_q}; + + // redist5_lOAdded_uid58_fpDivTest_q_3(DELAY,157) + dspba_delay_ver #( .width(24), .depth(3), .reset_kind("ASYNC") ) + redist5_lOAdded_uid58_fpDivTest_q_3 ( .xin(lOAdded_uid58_fpDivTest_q), .xout(redist5_lOAdded_uid58_fpDivTest_q_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // oFracXSE_bottomExtension_uid61_fpDivTest(CONSTANT,60) + assign oFracXSE_bottomExtension_uid61_fpDivTest_q = 2'b00; + + // oFracXSE_mergedSignalTM_uid63_fpDivTest(BITJOIN,62)@13 + assign oFracXSE_mergedSignalTM_uid63_fpDivTest_q = {redist5_lOAdded_uid58_fpDivTest_q_3_q, oFracXSE_bottomExtension_uid61_fpDivTest_q}; + + // yAddr_uid51_fpDivTest(BITSELECT,50)@0 + assign yAddr_uid51_fpDivTest_b = fracY_uid13_fpDivTest_b[22:14]; + + // memoryC2_uid118_invTables_lutmem(DUALMEM,147)@0 + 2 + // in j@20000000 + assign memoryC2_uid118_invTables_lutmem_aa = yAddr_uid51_fpDivTest_b; + assign memoryC2_uid118_invTables_lutmem_reset0 = areset; + altera_syncram #( + .ram_block_type("M20K"), + .operation_mode("ROM"), + .width_a(12), + .widthad_a(9), + .numwords_a(512), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .outdata_reg_a("CLOCK0"), + .outdata_aclr_a("CLEAR0"), + .clock_enable_input_a("NORMAL"), + .power_up_uninitialized("FALSE"), + .init_file("acl_fp_div_memoryC2_uid118_invTables_lutmem.hex"), + .init_file_layout("PORT_A"), + .intended_device_family("Arria 10") + ) memoryC2_uid118_invTables_lutmem_dmem ( + .clocken0(en[0]), + .aclr0(memoryC2_uid118_invTables_lutmem_reset0), + .clock0(clk), + .address_a(memoryC2_uid118_invTables_lutmem_aa), + .q_a(memoryC2_uid118_invTables_lutmem_ir), + .wren_a(), + .wren_b(), + .rden_a(), + .rden_b(), + .data_a(), + .data_b(), + .address_b(), + .clock1(), + .clocken1(), + .clocken2(), + .clocken3(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_b(), + .eccstatus() + ); + assign memoryC2_uid118_invTables_lutmem_r = memoryC2_uid118_invTables_lutmem_ir[11:0]; + + // yPE_uid52_fpDivTest(BITSELECT,51)@0 + assign yPE_uid52_fpDivTest_b = b[13:0]; + + // redist7_yPE_uid52_fpDivTest_b_2(DELAY,159) + dspba_delay_ver #( .width(14), .depth(2), .reset_kind("ASYNC") ) + redist7_yPE_uid52_fpDivTest_b_2 ( .xin(yPE_uid52_fpDivTest_b), .xout(redist7_yPE_uid52_fpDivTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // yT1_uid124_invPolyEval(BITSELECT,123)@2 + assign yT1_uid124_invPolyEval_b = redist7_yPE_uid52_fpDivTest_b_2_q[13:2]; + + // prodXY_uid140_pT1_uid125_invPolyEval_cma(CHAINMULTADD,149)@2 + 3 + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_reset = areset; + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_ena0 = en[0]; + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_ena1 = prodXY_uid140_pT1_uid125_invPolyEval_cma_ena0; + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_ena2 = prodXY_uid140_pT1_uid125_invPolyEval_cma_ena0; + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid140_pT1_uid125_invPolyEval_cma_a1[0][11:0]}); + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_p[0] = prodXY_uid140_pT1_uid125_invPolyEval_cma_l[0] * prodXY_uid140_pT1_uid125_invPolyEval_cma_c1[0]; + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_u[0] = prodXY_uid140_pT1_uid125_invPolyEval_cma_p[0][24:0]; + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_w[0] = prodXY_uid140_pT1_uid125_invPolyEval_cma_u[0]; + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_x[0] = prodXY_uid140_pT1_uid125_invPolyEval_cma_w[0]; + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_y[0] = prodXY_uid140_pT1_uid125_invPolyEval_cma_x[0]; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid140_pT1_uid125_invPolyEval_cma_a0 <= '{default: '0}; + prodXY_uid140_pT1_uid125_invPolyEval_cma_c0 <= '{default: '0}; + end + else + begin + if (prodXY_uid140_pT1_uid125_invPolyEval_cma_ena0 == 1'b1) + begin + prodXY_uid140_pT1_uid125_invPolyEval_cma_a0[0] <= yT1_uid124_invPolyEval_b; + prodXY_uid140_pT1_uid125_invPolyEval_cma_c0[0] <= memoryC2_uid118_invTables_lutmem_r; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid140_pT1_uid125_invPolyEval_cma_a1 <= '{default: '0}; + prodXY_uid140_pT1_uid125_invPolyEval_cma_c1 <= '{default: '0}; + end + else + begin + if (prodXY_uid140_pT1_uid125_invPolyEval_cma_ena2 == 1'b1) + begin + prodXY_uid140_pT1_uid125_invPolyEval_cma_a1 <= prodXY_uid140_pT1_uid125_invPolyEval_cma_a0; + prodXY_uid140_pT1_uid125_invPolyEval_cma_c1 <= prodXY_uid140_pT1_uid125_invPolyEval_cma_c0; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid140_pT1_uid125_invPolyEval_cma_s <= '{default: '0}; + end + else + begin + if (prodXY_uid140_pT1_uid125_invPolyEval_cma_ena1 == 1'b1) + begin + prodXY_uid140_pT1_uid125_invPolyEval_cma_s[0] <= prodXY_uid140_pT1_uid125_invPolyEval_cma_y[0]; + end + end + end + dspba_delay_ver #( .width(24), .depth(0), .reset_kind("ASYNC") ) + prodXY_uid140_pT1_uid125_invPolyEval_cma_delay ( .xin(prodXY_uid140_pT1_uid125_invPolyEval_cma_s[0][23:0]), .xout(prodXY_uid140_pT1_uid125_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign prodXY_uid140_pT1_uid125_invPolyEval_cma_q = prodXY_uid140_pT1_uid125_invPolyEval_cma_qq[23:0]; + + // osig_uid141_pT1_uid125_invPolyEval(BITSELECT,140)@5 + assign osig_uid141_pT1_uid125_invPolyEval_b = prodXY_uid140_pT1_uid125_invPolyEval_cma_q[23:11]; + + // highBBits_uid127_invPolyEval(BITSELECT,126)@5 + assign highBBits_uid127_invPolyEval_b = osig_uid141_pT1_uid125_invPolyEval_b[12:1]; + + // redist9_yAddr_uid51_fpDivTest_b_3(DELAY,161) + dspba_delay_ver #( .width(9), .depth(3), .reset_kind("ASYNC") ) + redist9_yAddr_uid51_fpDivTest_b_3 ( .xin(yAddr_uid51_fpDivTest_b), .xout(redist9_yAddr_uid51_fpDivTest_b_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // memoryC1_uid115_invTables_lutmem(DUALMEM,146)@3 + 2 + // in j@20000000 + assign memoryC1_uid115_invTables_lutmem_aa = redist9_yAddr_uid51_fpDivTest_b_3_q; + assign memoryC1_uid115_invTables_lutmem_reset0 = areset; + altera_syncram #( + .ram_block_type("M20K"), + .operation_mode("ROM"), + .width_a(21), + .widthad_a(9), + .numwords_a(512), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .outdata_reg_a("CLOCK0"), + .outdata_aclr_a("CLEAR0"), + .clock_enable_input_a("NORMAL"), + .power_up_uninitialized("FALSE"), + .init_file("acl_fp_div_memoryC1_uid115_invTables_lutmem.hex"), + .init_file_layout("PORT_A"), + .intended_device_family("Arria 10") + ) memoryC1_uid115_invTables_lutmem_dmem ( + .clocken0(en[0]), + .aclr0(memoryC1_uid115_invTables_lutmem_reset0), + .clock0(clk), + .address_a(memoryC1_uid115_invTables_lutmem_aa), + .q_a(memoryC1_uid115_invTables_lutmem_ir), + .wren_a(), + .wren_b(), + .rden_a(), + .rden_b(), + .data_a(), + .data_b(), + .address_b(), + .clock1(), + .clocken1(), + .clocken2(), + .clocken3(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_b(), + .eccstatus() + ); + assign memoryC1_uid115_invTables_lutmem_r = memoryC1_uid115_invTables_lutmem_ir[20:0]; + + // s1sumAHighB_uid128_invPolyEval(ADD,127)@5 + 1 + assign s1sumAHighB_uid128_invPolyEval_a = {{1{memoryC1_uid115_invTables_lutmem_r[20]}}, memoryC1_uid115_invTables_lutmem_r}; + assign s1sumAHighB_uid128_invPolyEval_b = {{10{highBBits_uid127_invPolyEval_b[11]}}, highBBits_uid127_invPolyEval_b}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + s1sumAHighB_uid128_invPolyEval_o <= 22'b0; + end + else if (en == 1'b1) + begin + s1sumAHighB_uid128_invPolyEval_o <= $signed(s1sumAHighB_uid128_invPolyEval_a) + $signed(s1sumAHighB_uid128_invPolyEval_b); + end + end + assign s1sumAHighB_uid128_invPolyEval_q = s1sumAHighB_uid128_invPolyEval_o[21:0]; + + // lowRangeB_uid126_invPolyEval(BITSELECT,125)@5 + assign lowRangeB_uid126_invPolyEval_in = osig_uid141_pT1_uid125_invPolyEval_b[0:0]; + assign lowRangeB_uid126_invPolyEval_b = lowRangeB_uid126_invPolyEval_in[0:0]; + + // redist1_lowRangeB_uid126_invPolyEval_b_1(DELAY,153) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist1_lowRangeB_uid126_invPolyEval_b_1 ( .xin(lowRangeB_uid126_invPolyEval_b), .xout(redist1_lowRangeB_uid126_invPolyEval_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // s1_uid129_invPolyEval(BITJOIN,128)@6 + assign s1_uid129_invPolyEval_q = {s1sumAHighB_uid128_invPolyEval_q, redist1_lowRangeB_uid126_invPolyEval_b_1_q}; + + // redist8_yPE_uid52_fpDivTest_b_6_notEnable(LOGICAL,180) + assign redist8_yPE_uid52_fpDivTest_b_6_notEnable_q = ~ (en); + + // redist8_yPE_uid52_fpDivTest_b_6_nor(LOGICAL,181) + assign redist8_yPE_uid52_fpDivTest_b_6_nor_q = ~ (redist8_yPE_uid52_fpDivTest_b_6_notEnable_q | redist8_yPE_uid52_fpDivTest_b_6_sticky_ena_q); + + // redist8_yPE_uid52_fpDivTest_b_6_mem_last(CONSTANT,177) + assign redist8_yPE_uid52_fpDivTest_b_6_mem_last_q = 2'b01; + + // redist8_yPE_uid52_fpDivTest_b_6_cmp(LOGICAL,178) + assign redist8_yPE_uid52_fpDivTest_b_6_cmp_q = redist8_yPE_uid52_fpDivTest_b_6_mem_last_q == redist8_yPE_uid52_fpDivTest_b_6_rdmux_q ? 1'b1 : 1'b0; + + // redist8_yPE_uid52_fpDivTest_b_6_cmpReg(REG,179) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist8_yPE_uid52_fpDivTest_b_6_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist8_yPE_uid52_fpDivTest_b_6_cmpReg_q <= redist8_yPE_uid52_fpDivTest_b_6_cmp_q; + end + end + + // redist8_yPE_uid52_fpDivTest_b_6_sticky_ena(REG,182) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist8_yPE_uid52_fpDivTest_b_6_sticky_ena_q <= 1'b0; + end + else if (redist8_yPE_uid52_fpDivTest_b_6_nor_q == 1'b1) + begin + redist8_yPE_uid52_fpDivTest_b_6_sticky_ena_q <= redist8_yPE_uid52_fpDivTest_b_6_cmpReg_q; + end + end + + // redist8_yPE_uid52_fpDivTest_b_6_enaAnd(LOGICAL,183) + assign redist8_yPE_uid52_fpDivTest_b_6_enaAnd_q = redist8_yPE_uid52_fpDivTest_b_6_sticky_ena_q & en; + + // redist8_yPE_uid52_fpDivTest_b_6_rdcnt(COUNTER,174) + // low=0, high=2, step=1, init=0 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist8_yPE_uid52_fpDivTest_b_6_rdcnt_i <= 2'd0; + redist8_yPE_uid52_fpDivTest_b_6_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist8_yPE_uid52_fpDivTest_b_6_rdcnt_i == 2'd1) + begin + redist8_yPE_uid52_fpDivTest_b_6_rdcnt_eq <= 1'b1; + end + else + begin + redist8_yPE_uid52_fpDivTest_b_6_rdcnt_eq <= 1'b0; + end + if (redist8_yPE_uid52_fpDivTest_b_6_rdcnt_eq == 1'b1) + begin + redist8_yPE_uid52_fpDivTest_b_6_rdcnt_i <= $unsigned(redist8_yPE_uid52_fpDivTest_b_6_rdcnt_i) + $unsigned(2'd2); + end + else + begin + redist8_yPE_uid52_fpDivTest_b_6_rdcnt_i <= $unsigned(redist8_yPE_uid52_fpDivTest_b_6_rdcnt_i) + $unsigned(2'd1); + end + end + end + assign redist8_yPE_uid52_fpDivTest_b_6_rdcnt_q = redist8_yPE_uid52_fpDivTest_b_6_rdcnt_i[1:0]; + + // redist8_yPE_uid52_fpDivTest_b_6_rdmux(MUX,175) + assign redist8_yPE_uid52_fpDivTest_b_6_rdmux_s = en; + always @(redist8_yPE_uid52_fpDivTest_b_6_rdmux_s or redist8_yPE_uid52_fpDivTest_b_6_wraddr_q or redist8_yPE_uid52_fpDivTest_b_6_rdcnt_q) + begin + unique case (redist8_yPE_uid52_fpDivTest_b_6_rdmux_s) + 1'b0 : redist8_yPE_uid52_fpDivTest_b_6_rdmux_q = redist8_yPE_uid52_fpDivTest_b_6_wraddr_q; + 1'b1 : redist8_yPE_uid52_fpDivTest_b_6_rdmux_q = redist8_yPE_uid52_fpDivTest_b_6_rdcnt_q; + default : redist8_yPE_uid52_fpDivTest_b_6_rdmux_q = 2'b0; + endcase + end + + // redist8_yPE_uid52_fpDivTest_b_6_wraddr(REG,176) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist8_yPE_uid52_fpDivTest_b_6_wraddr_q <= 2'b10; + end + else + begin + redist8_yPE_uid52_fpDivTest_b_6_wraddr_q <= redist8_yPE_uid52_fpDivTest_b_6_rdmux_q; + end + end + + // redist8_yPE_uid52_fpDivTest_b_6_mem(DUALMEM,173) + assign redist8_yPE_uid52_fpDivTest_b_6_mem_ia = redist7_yPE_uid52_fpDivTest_b_2_q; + assign redist8_yPE_uid52_fpDivTest_b_6_mem_aa = redist8_yPE_uid52_fpDivTest_b_6_wraddr_q; + assign redist8_yPE_uid52_fpDivTest_b_6_mem_ab = redist8_yPE_uid52_fpDivTest_b_6_rdmux_q; + assign redist8_yPE_uid52_fpDivTest_b_6_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(14), + .widthad_a(2), + .numwords_a(3), + .width_b(14), + .widthad_b(2), + .numwords_b(3), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_aclr_b("CLEAR1"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Arria 10") + ) redist8_yPE_uid52_fpDivTest_b_6_mem_dmem ( + .clocken1(redist8_yPE_uid52_fpDivTest_b_6_enaAnd_q[0]), + .clocken0(VCC_q[0]), + .clock0(clk), + .aclr1(redist8_yPE_uid52_fpDivTest_b_6_mem_reset0), + .clock1(clk), + .address_a(redist8_yPE_uid52_fpDivTest_b_6_mem_aa), + .data_a(redist8_yPE_uid52_fpDivTest_b_6_mem_ia), + .wren_a(en[0]), + .address_b(redist8_yPE_uid52_fpDivTest_b_6_mem_ab), + .q_b(redist8_yPE_uid52_fpDivTest_b_6_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist8_yPE_uid52_fpDivTest_b_6_mem_q = redist8_yPE_uid52_fpDivTest_b_6_mem_iq[13:0]; + + // prodXY_uid143_pT2_uid131_invPolyEval_cma(CHAINMULTADD,150)@6 + 3 + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_reset = areset; + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_ena0 = en[0]; + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_ena1 = prodXY_uid143_pT2_uid131_invPolyEval_cma_ena0; + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_ena2 = prodXY_uid143_pT2_uid131_invPolyEval_cma_ena0; + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid143_pT2_uid131_invPolyEval_cma_a1[0][13:0]}); + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_p[0] = prodXY_uid143_pT2_uid131_invPolyEval_cma_l[0] * prodXY_uid143_pT2_uid131_invPolyEval_cma_c1[0]; + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_u[0] = prodXY_uid143_pT2_uid131_invPolyEval_cma_p[0][37:0]; + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_w[0] = prodXY_uid143_pT2_uid131_invPolyEval_cma_u[0]; + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_x[0] = prodXY_uid143_pT2_uid131_invPolyEval_cma_w[0]; + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_y[0] = prodXY_uid143_pT2_uid131_invPolyEval_cma_x[0]; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid143_pT2_uid131_invPolyEval_cma_a0 <= '{default: '0}; + prodXY_uid143_pT2_uid131_invPolyEval_cma_c0 <= '{default: '0}; + end + else + begin + if (prodXY_uid143_pT2_uid131_invPolyEval_cma_ena0 == 1'b1) + begin + prodXY_uid143_pT2_uid131_invPolyEval_cma_a0[0] <= redist8_yPE_uid52_fpDivTest_b_6_mem_q; + prodXY_uid143_pT2_uid131_invPolyEval_cma_c0[0] <= s1_uid129_invPolyEval_q; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid143_pT2_uid131_invPolyEval_cma_a1 <= '{default: '0}; + prodXY_uid143_pT2_uid131_invPolyEval_cma_c1 <= '{default: '0}; + end + else + begin + if (prodXY_uid143_pT2_uid131_invPolyEval_cma_ena2 == 1'b1) + begin + prodXY_uid143_pT2_uid131_invPolyEval_cma_a1 <= prodXY_uid143_pT2_uid131_invPolyEval_cma_a0; + prodXY_uid143_pT2_uid131_invPolyEval_cma_c1 <= prodXY_uid143_pT2_uid131_invPolyEval_cma_c0; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid143_pT2_uid131_invPolyEval_cma_s <= '{default: '0}; + end + else + begin + if (prodXY_uid143_pT2_uid131_invPolyEval_cma_ena1 == 1'b1) + begin + prodXY_uid143_pT2_uid131_invPolyEval_cma_s[0] <= prodXY_uid143_pT2_uid131_invPolyEval_cma_y[0]; + end + end + end + dspba_delay_ver #( .width(37), .depth(0), .reset_kind("ASYNC") ) + prodXY_uid143_pT2_uid131_invPolyEval_cma_delay ( .xin(prodXY_uid143_pT2_uid131_invPolyEval_cma_s[0][36:0]), .xout(prodXY_uid143_pT2_uid131_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign prodXY_uid143_pT2_uid131_invPolyEval_cma_q = prodXY_uid143_pT2_uid131_invPolyEval_cma_qq[36:0]; + + // osig_uid144_pT2_uid131_invPolyEval(BITSELECT,143)@9 + assign osig_uid144_pT2_uid131_invPolyEval_b = prodXY_uid143_pT2_uid131_invPolyEval_cma_q[36:13]; + + // highBBits_uid133_invPolyEval(BITSELECT,132)@9 + assign highBBits_uid133_invPolyEval_b = osig_uid144_pT2_uid131_invPolyEval_b[23:2]; + + // redist10_yAddr_uid51_fpDivTest_b_7(DELAY,162) + dspba_delay_ver #( .width(9), .depth(4), .reset_kind("ASYNC") ) + redist10_yAddr_uid51_fpDivTest_b_7 ( .xin(redist9_yAddr_uid51_fpDivTest_b_3_q), .xout(redist10_yAddr_uid51_fpDivTest_b_7_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // memoryC0_uid112_invTables_lutmem(DUALMEM,145)@7 + 2 + // in j@20000000 + assign memoryC0_uid112_invTables_lutmem_aa = redist10_yAddr_uid51_fpDivTest_b_7_q; + assign memoryC0_uid112_invTables_lutmem_reset0 = areset; + altera_syncram #( + .ram_block_type("M20K"), + .operation_mode("ROM"), + .width_a(31), + .widthad_a(9), + .numwords_a(512), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .outdata_reg_a("CLOCK0"), + .outdata_aclr_a("CLEAR0"), + .clock_enable_input_a("NORMAL"), + .power_up_uninitialized("FALSE"), + .init_file("acl_fp_div_memoryC0_uid112_invTables_lutmem.hex"), + .init_file_layout("PORT_A"), + .intended_device_family("Arria 10") + ) memoryC0_uid112_invTables_lutmem_dmem ( + .clocken0(en[0]), + .aclr0(memoryC0_uid112_invTables_lutmem_reset0), + .clock0(clk), + .address_a(memoryC0_uid112_invTables_lutmem_aa), + .q_a(memoryC0_uid112_invTables_lutmem_ir), + .wren_a(), + .wren_b(), + .rden_a(), + .rden_b(), + .data_a(), + .data_b(), + .address_b(), + .clock1(), + .clocken1(), + .clocken2(), + .clocken3(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_b(), + .eccstatus() + ); + assign memoryC0_uid112_invTables_lutmem_r = memoryC0_uid112_invTables_lutmem_ir[30:0]; + + // s2sumAHighB_uid134_invPolyEval(ADD,133)@9 + assign s2sumAHighB_uid134_invPolyEval_a = {{1{memoryC0_uid112_invTables_lutmem_r[30]}}, memoryC0_uid112_invTables_lutmem_r}; + assign s2sumAHighB_uid134_invPolyEval_b = {{10{highBBits_uid133_invPolyEval_b[21]}}, highBBits_uid133_invPolyEval_b}; + assign s2sumAHighB_uid134_invPolyEval_o = $signed(s2sumAHighB_uid134_invPolyEval_a) + $signed(s2sumAHighB_uid134_invPolyEval_b); + assign s2sumAHighB_uid134_invPolyEval_q = s2sumAHighB_uid134_invPolyEval_o[31:0]; + + // lowRangeB_uid132_invPolyEval(BITSELECT,131)@9 + assign lowRangeB_uid132_invPolyEval_in = osig_uid144_pT2_uid131_invPolyEval_b[1:0]; + assign lowRangeB_uid132_invPolyEval_b = lowRangeB_uid132_invPolyEval_in[1:0]; + + // s2_uid135_invPolyEval(BITJOIN,134)@9 + assign s2_uid135_invPolyEval_q = {s2sumAHighB_uid134_invPolyEval_q, lowRangeB_uid132_invPolyEval_b}; + + // invY_uid54_fpDivTest_merged_bit_select(BITSELECT,151)@9 + assign invY_uid54_fpDivTest_merged_bit_select_in = s2_uid135_invPolyEval_q[31:0]; + assign invY_uid54_fpDivTest_merged_bit_select_b = invY_uid54_fpDivTest_merged_bit_select_in[30:5]; + assign invY_uid54_fpDivTest_merged_bit_select_c = invY_uid54_fpDivTest_merged_bit_select_in[31:31]; + + // redist0_invY_uid54_fpDivTest_merged_bit_select_b_1(DELAY,152) + dspba_delay_ver #( .width(26), .depth(1), .reset_kind("ASYNC") ) + redist0_invY_uid54_fpDivTest_merged_bit_select_b_1 ( .xin(invY_uid54_fpDivTest_merged_bit_select_b), .xout(redist0_invY_uid54_fpDivTest_merged_bit_select_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // GND(CONSTANT,0) + assign GND_q = 1'b0; + + // prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma(CHAINMULTADD,148)@10 + 3 + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_reset = areset; + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena0 = en[0]; + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena1 = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena0; + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena2 = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena0; + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_p[0] = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a1[0] * prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c1[0]; + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_u[0] = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_p[0][49:0]; + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_w[0] = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_u[0]; + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_x[0] = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_w[0]; + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_y[0] = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_x[0]; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a0 <= '{default: '0}; + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c0 <= '{default: '0}; + end + else + begin + if (prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena0 == 1'b1) + begin + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a0[0] <= redist0_invY_uid54_fpDivTest_merged_bit_select_b_1_q; + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c0[0] <= lOAdded_uid58_fpDivTest_q; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a1 <= '{default: '0}; + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c1 <= '{default: '0}; + end + else + begin + if (prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena2 == 1'b1) + begin + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a1 <= prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_a0; + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c1 <= prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_c0; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_s <= '{default: '0}; + end + else + begin + if (prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_ena1 == 1'b1) + begin + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_s[0] <= prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_y[0]; + end + end + end + dspba_delay_ver #( .width(50), .depth(0), .reset_kind("ASYNC") ) + prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_delay ( .xin(prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_s[0][49:0]), .xout(prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_q = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_qq[49:0]; + + // osig_uid138_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,137)@13 + assign osig_uid138_prodDivPreNormProd_uid60_fpDivTest_b = prodXY_uid137_prodDivPreNormProd_uid60_fpDivTest_cma_q[49:24]; + + // updatedY_uid16_fpDivTest(BITJOIN,15)@0 + assign updatedY_uid16_fpDivTest_q = {GND_q, paddingY_uid15_fpDivTest_q}; + + // fracYZero_uid15_fpDivTest(LOGICAL,16)@0 + 1 + assign fracYZero_uid15_fpDivTest_a = {1'b0, fracY_uid13_fpDivTest_b}; + assign fracYZero_uid15_fpDivTest_qi = fracYZero_uid15_fpDivTest_a == updatedY_uid16_fpDivTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + fracYZero_uid15_fpDivTest_delay ( .xin(fracYZero_uid15_fpDivTest_qi), .xout(fracYZero_uid15_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist19_fracYZero_uid15_fpDivTest_q_9(DELAY,171) + dspba_delay_ver #( .width(1), .depth(8), .reset_kind("ASYNC") ) + redist19_fracYZero_uid15_fpDivTest_q_9 ( .xin(fracYZero_uid15_fpDivTest_q), .xout(redist19_fracYZero_uid15_fpDivTest_q_9_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // fracYPostZ_uid56_fpDivTest(LOGICAL,55)@9 + 1 + assign fracYPostZ_uid56_fpDivTest_qi = redist19_fracYZero_uid15_fpDivTest_q_9_q | invY_uid54_fpDivTest_merged_bit_select_c; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + fracYPostZ_uid56_fpDivTest_delay ( .xin(fracYPostZ_uid56_fpDivTest_qi), .xout(fracYPostZ_uid56_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist6_fracYPostZ_uid56_fpDivTest_q_4(DELAY,158) + dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") ) + redist6_fracYPostZ_uid56_fpDivTest_q_4 ( .xin(fracYPostZ_uid56_fpDivTest_q), .xout(redist6_fracYPostZ_uid56_fpDivTest_q_4_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // divValPreNormTrunc_uid66_fpDivTest(MUX,65)@13 + assign divValPreNormTrunc_uid66_fpDivTest_s = redist6_fracYPostZ_uid56_fpDivTest_q_4_q; + always @(divValPreNormTrunc_uid66_fpDivTest_s or en or osig_uid138_prodDivPreNormProd_uid60_fpDivTest_b or oFracXSE_mergedSignalTM_uid63_fpDivTest_q) + begin + unique case (divValPreNormTrunc_uid66_fpDivTest_s) + 1'b0 : divValPreNormTrunc_uid66_fpDivTest_q = osig_uid138_prodDivPreNormProd_uid60_fpDivTest_b; + 1'b1 : divValPreNormTrunc_uid66_fpDivTest_q = oFracXSE_mergedSignalTM_uid63_fpDivTest_q; + default : divValPreNormTrunc_uid66_fpDivTest_q = 26'b0; + endcase + end + + // norm_uid67_fpDivTest(BITSELECT,66)@13 + assign norm_uid67_fpDivTest_b = divValPreNormTrunc_uid66_fpDivTest_q[25:25]; + + // redist4_norm_uid67_fpDivTest_b_1(DELAY,156) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist4_norm_uid67_fpDivTest_b_1 ( .xin(norm_uid67_fpDivTest_b), .xout(redist4_norm_uid67_fpDivTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // rndOp_uid75_fpDivTest(BITJOIN,74)@14 + assign rndOp_uid75_fpDivTest_q = {redist4_norm_uid67_fpDivTest_b_1_q, paddingY_uid15_fpDivTest_q, VCC_q}; + + // cstBiasM1_uid6_fpDivTest(CONSTANT,5) + assign cstBiasM1_uid6_fpDivTest_q = 8'b01111110; + + // redist11_expXmY_uid47_fpDivTest_q_13_notEnable(LOGICAL,192) + assign redist11_expXmY_uid47_fpDivTest_q_13_notEnable_q = ~ (en); + + // redist11_expXmY_uid47_fpDivTest_q_13_nor(LOGICAL,193) + assign redist11_expXmY_uid47_fpDivTest_q_13_nor_q = ~ (redist11_expXmY_uid47_fpDivTest_q_13_notEnable_q | redist11_expXmY_uid47_fpDivTest_q_13_sticky_ena_q); + + // redist11_expXmY_uid47_fpDivTest_q_13_mem_last(CONSTANT,189) + assign redist11_expXmY_uid47_fpDivTest_q_13_mem_last_q = 5'b01000; + + // redist11_expXmY_uid47_fpDivTest_q_13_cmp(LOGICAL,190) + assign redist11_expXmY_uid47_fpDivTest_q_13_cmp_b = {1'b0, redist11_expXmY_uid47_fpDivTest_q_13_rdmux_q}; + assign redist11_expXmY_uid47_fpDivTest_q_13_cmp_q = redist11_expXmY_uid47_fpDivTest_q_13_mem_last_q == redist11_expXmY_uid47_fpDivTest_q_13_cmp_b ? 1'b1 : 1'b0; + + // redist11_expXmY_uid47_fpDivTest_q_13_cmpReg(REG,191) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist11_expXmY_uid47_fpDivTest_q_13_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist11_expXmY_uid47_fpDivTest_q_13_cmpReg_q <= redist11_expXmY_uid47_fpDivTest_q_13_cmp_q; + end + end + + // redist11_expXmY_uid47_fpDivTest_q_13_sticky_ena(REG,194) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist11_expXmY_uid47_fpDivTest_q_13_sticky_ena_q <= 1'b0; + end + else if (redist11_expXmY_uid47_fpDivTest_q_13_nor_q == 1'b1) + begin + redist11_expXmY_uid47_fpDivTest_q_13_sticky_ena_q <= redist11_expXmY_uid47_fpDivTest_q_13_cmpReg_q; + end + end + + // redist11_expXmY_uid47_fpDivTest_q_13_enaAnd(LOGICAL,195) + assign redist11_expXmY_uid47_fpDivTest_q_13_enaAnd_q = redist11_expXmY_uid47_fpDivTest_q_13_sticky_ena_q & en; + + // redist11_expXmY_uid47_fpDivTest_q_13_rdcnt(COUNTER,186) + // low=0, high=9, step=1, init=0 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist11_expXmY_uid47_fpDivTest_q_13_rdcnt_i <= 4'd0; + redist11_expXmY_uid47_fpDivTest_q_13_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist11_expXmY_uid47_fpDivTest_q_13_rdcnt_i == 4'd8) + begin + redist11_expXmY_uid47_fpDivTest_q_13_rdcnt_eq <= 1'b1; + end + else + begin + redist11_expXmY_uid47_fpDivTest_q_13_rdcnt_eq <= 1'b0; + end + if (redist11_expXmY_uid47_fpDivTest_q_13_rdcnt_eq == 1'b1) + begin + redist11_expXmY_uid47_fpDivTest_q_13_rdcnt_i <= $unsigned(redist11_expXmY_uid47_fpDivTest_q_13_rdcnt_i) + $unsigned(4'd7); + end + else + begin + redist11_expXmY_uid47_fpDivTest_q_13_rdcnt_i <= $unsigned(redist11_expXmY_uid47_fpDivTest_q_13_rdcnt_i) + $unsigned(4'd1); + end + end + end + assign redist11_expXmY_uid47_fpDivTest_q_13_rdcnt_q = redist11_expXmY_uid47_fpDivTest_q_13_rdcnt_i[3:0]; + + // redist11_expXmY_uid47_fpDivTest_q_13_rdmux(MUX,187) + assign redist11_expXmY_uid47_fpDivTest_q_13_rdmux_s = en; + always @(redist11_expXmY_uid47_fpDivTest_q_13_rdmux_s or redist11_expXmY_uid47_fpDivTest_q_13_wraddr_q or redist11_expXmY_uid47_fpDivTest_q_13_rdcnt_q) + begin + unique case (redist11_expXmY_uid47_fpDivTest_q_13_rdmux_s) + 1'b0 : redist11_expXmY_uid47_fpDivTest_q_13_rdmux_q = redist11_expXmY_uid47_fpDivTest_q_13_wraddr_q; + 1'b1 : redist11_expXmY_uid47_fpDivTest_q_13_rdmux_q = redist11_expXmY_uid47_fpDivTest_q_13_rdcnt_q; + default : redist11_expXmY_uid47_fpDivTest_q_13_rdmux_q = 4'b0; + endcase + end + + // expXmY_uid47_fpDivTest(SUB,46)@0 + 1 + assign expXmY_uid47_fpDivTest_a = {1'b0, expX_uid9_fpDivTest_b}; + assign expXmY_uid47_fpDivTest_b = {1'b0, expY_uid12_fpDivTest_b}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + expXmY_uid47_fpDivTest_o <= 9'b0; + end + else if (en == 1'b1) + begin + expXmY_uid47_fpDivTest_o <= $unsigned(expXmY_uid47_fpDivTest_a) - $unsigned(expXmY_uid47_fpDivTest_b); + end + end + assign expXmY_uid47_fpDivTest_q = expXmY_uid47_fpDivTest_o[8:0]; + + // redist11_expXmY_uid47_fpDivTest_q_13_wraddr(REG,188) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist11_expXmY_uid47_fpDivTest_q_13_wraddr_q <= 4'b1001; + end + else + begin + redist11_expXmY_uid47_fpDivTest_q_13_wraddr_q <= redist11_expXmY_uid47_fpDivTest_q_13_rdmux_q; + end + end + + // redist11_expXmY_uid47_fpDivTest_q_13_mem(DUALMEM,185) + assign redist11_expXmY_uid47_fpDivTest_q_13_mem_ia = expXmY_uid47_fpDivTest_q; + assign redist11_expXmY_uid47_fpDivTest_q_13_mem_aa = redist11_expXmY_uid47_fpDivTest_q_13_wraddr_q; + assign redist11_expXmY_uid47_fpDivTest_q_13_mem_ab = redist11_expXmY_uid47_fpDivTest_q_13_rdmux_q; + assign redist11_expXmY_uid47_fpDivTest_q_13_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(9), + .widthad_a(4), + .numwords_a(10), + .width_b(9), + .widthad_b(4), + .numwords_b(10), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_aclr_b("CLEAR1"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Arria 10") + ) redist11_expXmY_uid47_fpDivTest_q_13_mem_dmem ( + .clocken1(redist11_expXmY_uid47_fpDivTest_q_13_enaAnd_q[0]), + .clocken0(VCC_q[0]), + .clock0(clk), + .aclr1(redist11_expXmY_uid47_fpDivTest_q_13_mem_reset0), + .clock1(clk), + .address_a(redist11_expXmY_uid47_fpDivTest_q_13_mem_aa), + .data_a(redist11_expXmY_uid47_fpDivTest_q_13_mem_ia), + .wren_a(en[0]), + .address_b(redist11_expXmY_uid47_fpDivTest_q_13_mem_ab), + .q_b(redist11_expXmY_uid47_fpDivTest_q_13_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist11_expXmY_uid47_fpDivTest_q_13_mem_q = redist11_expXmY_uid47_fpDivTest_q_13_mem_iq[8:0]; + + // redist11_expXmY_uid47_fpDivTest_q_13_outputreg(DELAY,184) + dspba_delay_ver #( .width(9), .depth(1), .reset_kind("ASYNC") ) + redist11_expXmY_uid47_fpDivTest_q_13_outputreg ( .xin(redist11_expXmY_uid47_fpDivTest_q_13_mem_q), .xout(redist11_expXmY_uid47_fpDivTest_q_13_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expR_uid48_fpDivTest(ADD,47)@13 + 1 + assign expR_uid48_fpDivTest_a = {{2{redist11_expXmY_uid47_fpDivTest_q_13_outputreg_q[8]}}, redist11_expXmY_uid47_fpDivTest_q_13_outputreg_q}; + assign expR_uid48_fpDivTest_b = {3'b000, cstBiasM1_uid6_fpDivTest_q}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + expR_uid48_fpDivTest_o <= 11'b0; + end + else if (en == 1'b1) + begin + expR_uid48_fpDivTest_o <= $signed(expR_uid48_fpDivTest_a) + $signed(expR_uid48_fpDivTest_b); + end + end + assign expR_uid48_fpDivTest_q = expR_uid48_fpDivTest_o[9:0]; + + // divValPreNormHigh_uid68_fpDivTest(BITSELECT,67)@13 + assign divValPreNormHigh_uid68_fpDivTest_in = divValPreNormTrunc_uid66_fpDivTest_q[24:0]; + assign divValPreNormHigh_uid68_fpDivTest_b = divValPreNormHigh_uid68_fpDivTest_in[24:1]; + + // divValPreNormLow_uid69_fpDivTest(BITSELECT,68)@13 + assign divValPreNormLow_uid69_fpDivTest_in = divValPreNormTrunc_uid66_fpDivTest_q[23:0]; + assign divValPreNormLow_uid69_fpDivTest_b = divValPreNormLow_uid69_fpDivTest_in[23:0]; + + // normFracRnd_uid70_fpDivTest(MUX,69)@13 + 1 + assign normFracRnd_uid70_fpDivTest_s = norm_uid67_fpDivTest_b; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + normFracRnd_uid70_fpDivTest_q <= 24'b0; + end + else if (en == 1'b1) + begin + unique case (normFracRnd_uid70_fpDivTest_s) + 1'b0 : normFracRnd_uid70_fpDivTest_q <= divValPreNormLow_uid69_fpDivTest_b; + 1'b1 : normFracRnd_uid70_fpDivTest_q <= divValPreNormHigh_uid68_fpDivTest_b; + default : normFracRnd_uid70_fpDivTest_q <= 24'b0; + endcase + end + end + + // expFracRnd_uid71_fpDivTest(BITJOIN,70)@14 + assign expFracRnd_uid71_fpDivTest_q = {expR_uid48_fpDivTest_q, normFracRnd_uid70_fpDivTest_q}; + + // expFracPostRnd_uid76_fpDivTest(ADD,75)@14 + 1 + assign expFracPostRnd_uid76_fpDivTest_a = {{2{expFracRnd_uid71_fpDivTest_q[33]}}, expFracRnd_uid71_fpDivTest_q}; + assign expFracPostRnd_uid76_fpDivTest_b = {11'b00000000000, rndOp_uid75_fpDivTest_q}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + expFracPostRnd_uid76_fpDivTest_o <= 36'b0; + end + else if (en == 1'b1) + begin + expFracPostRnd_uid76_fpDivTest_o <= $signed(expFracPostRnd_uid76_fpDivTest_a) + $signed(expFracPostRnd_uid76_fpDivTest_b); + end + end + assign expFracPostRnd_uid76_fpDivTest_q = expFracPostRnd_uid76_fpDivTest_o[34:0]; + + // excRPreExc_uid79_fpDivTest(BITSELECT,78)@15 + assign excRPreExc_uid79_fpDivTest_in = expFracPostRnd_uid76_fpDivTest_q[31:0]; + assign excRPreExc_uid79_fpDivTest_b = excRPreExc_uid79_fpDivTest_in[31:24]; + + // redist2_excRPreExc_uid79_fpDivTest_b_1(DELAY,154) + dspba_delay_ver #( .width(8), .depth(1), .reset_kind("ASYNC") ) + redist2_excRPreExc_uid79_fpDivTest_b_1 ( .xin(excRPreExc_uid79_fpDivTest_b), .xout(redist2_excRPreExc_uid79_fpDivTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // invExpXIsMax_uid43_fpDivTest(LOGICAL,42)@15 + assign invExpXIsMax_uid43_fpDivTest_q = ~ (redist14_expXIsMax_uid38_fpDivTest_q_15_q); + + // InvExpXIsZero_uid44_fpDivTest(LOGICAL,43)@15 + assign InvExpXIsZero_uid44_fpDivTest_q = ~ (redist15_excZ_y_uid37_fpDivTest_q_15_q); + + // excR_y_uid45_fpDivTest(LOGICAL,44)@15 + assign excR_y_uid45_fpDivTest_q = InvExpXIsZero_uid44_fpDivTest_q & invExpXIsMax_uid43_fpDivTest_q; + + // excXIYR_uid93_fpDivTest(LOGICAL,92)@15 + assign excXIYR_uid93_fpDivTest_q = excI_x_uid27_fpDivTest_q & excR_y_uid45_fpDivTest_q; + + // excXIYZ_uid92_fpDivTest(LOGICAL,91)@15 + assign excXIYZ_uid92_fpDivTest_q = excI_x_uid27_fpDivTest_q & redist15_excZ_y_uid37_fpDivTest_q_15_q; + + // expRExt_uid80_fpDivTest(BITSELECT,79)@15 + assign expRExt_uid80_fpDivTest_b = expFracPostRnd_uid76_fpDivTest_q[34:24]; + + // expOvf_uid84_fpDivTest(COMPARE,83)@15 + assign expOvf_uid84_fpDivTest_a = {{2{expRExt_uid80_fpDivTest_b[10]}}, expRExt_uid80_fpDivTest_b}; + assign expOvf_uid84_fpDivTest_b = {5'b00000, cstAllOWE_uid18_fpDivTest_q}; + assign expOvf_uid84_fpDivTest_o = $signed(expOvf_uid84_fpDivTest_a) - $signed(expOvf_uid84_fpDivTest_b); + assign expOvf_uid84_fpDivTest_n[0] = ~ (expOvf_uid84_fpDivTest_o[12]); + + // invExpXIsMax_uid29_fpDivTest(LOGICAL,28)@15 + assign invExpXIsMax_uid29_fpDivTest_q = ~ (redist17_expXIsMax_uid24_fpDivTest_q_15_q); + + // InvExpXIsZero_uid30_fpDivTest(LOGICAL,29)@15 + assign InvExpXIsZero_uid30_fpDivTest_q = ~ (redist18_excZ_x_uid23_fpDivTest_q_15_q); + + // excR_x_uid31_fpDivTest(LOGICAL,30)@15 + assign excR_x_uid31_fpDivTest_q = InvExpXIsZero_uid30_fpDivTest_q & invExpXIsMax_uid29_fpDivTest_q; + + // excXRYROvf_uid91_fpDivTest(LOGICAL,90)@15 + assign excXRYROvf_uid91_fpDivTest_q = excR_x_uid31_fpDivTest_q & excR_y_uid45_fpDivTest_q & expOvf_uid84_fpDivTest_n; + + // excXRYZ_uid90_fpDivTest(LOGICAL,89)@15 + assign excXRYZ_uid90_fpDivTest_q = excR_x_uid31_fpDivTest_q & redist15_excZ_y_uid37_fpDivTest_q_15_q; + + // excRInf_uid94_fpDivTest(LOGICAL,93)@15 + 1 + assign excRInf_uid94_fpDivTest_qi = excXRYZ_uid90_fpDivTest_q | excXRYROvf_uid91_fpDivTest_q | excXIYZ_uid92_fpDivTest_q | excXIYR_uid93_fpDivTest_q; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + excRInf_uid94_fpDivTest_delay ( .xin(excRInf_uid94_fpDivTest_qi), .xout(excRInf_uid94_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // xRegOrZero_uid87_fpDivTest(LOGICAL,86)@15 + assign xRegOrZero_uid87_fpDivTest_q = excR_x_uid31_fpDivTest_q | redist18_excZ_x_uid23_fpDivTest_q_15_q; + + // regOrZeroOverInf_uid88_fpDivTest(LOGICAL,87)@15 + assign regOrZeroOverInf_uid88_fpDivTest_q = xRegOrZero_uid87_fpDivTest_q & excI_y_uid41_fpDivTest_q; + + // expUdf_uid81_fpDivTest(COMPARE,80)@15 + assign expUdf_uid81_fpDivTest_a = {12'b000000000000, GND_q}; + assign expUdf_uid81_fpDivTest_b = {{2{expRExt_uid80_fpDivTest_b[10]}}, expRExt_uid80_fpDivTest_b}; + assign expUdf_uid81_fpDivTest_o = $signed(expUdf_uid81_fpDivTest_a) - $signed(expUdf_uid81_fpDivTest_b); + assign expUdf_uid81_fpDivTest_n[0] = ~ (expUdf_uid81_fpDivTest_o[12]); + + // regOverRegWithUf_uid86_fpDivTest(LOGICAL,85)@15 + assign regOverRegWithUf_uid86_fpDivTest_q = expUdf_uid81_fpDivTest_n & excR_x_uid31_fpDivTest_q & excR_y_uid45_fpDivTest_q; + + // zeroOverReg_uid85_fpDivTest(LOGICAL,84)@15 + assign zeroOverReg_uid85_fpDivTest_q = redist18_excZ_x_uid23_fpDivTest_q_15_q & excR_y_uid45_fpDivTest_q; + + // excRZero_uid89_fpDivTest(LOGICAL,88)@15 + 1 + assign excRZero_uid89_fpDivTest_qi = zeroOverReg_uid85_fpDivTest_q | regOverRegWithUf_uid86_fpDivTest_q | regOrZeroOverInf_uid88_fpDivTest_q; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + excRZero_uid89_fpDivTest_delay ( .xin(excRZero_uid89_fpDivTest_qi), .xout(excRZero_uid89_fpDivTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // concExc_uid98_fpDivTest(BITJOIN,97)@16 + assign concExc_uid98_fpDivTest_q = {excRNaN_uid97_fpDivTest_q, excRInf_uid94_fpDivTest_q, excRZero_uid89_fpDivTest_q}; + + // excREnc_uid99_fpDivTest(LOOKUP,98)@16 + always @(concExc_uid98_fpDivTest_q) + begin + // Begin reserved scope level + unique case (concExc_uid98_fpDivTest_q) + 3'b000 : excREnc_uid99_fpDivTest_q = 2'b01; + 3'b001 : excREnc_uid99_fpDivTest_q = 2'b00; + 3'b010 : excREnc_uid99_fpDivTest_q = 2'b10; + 3'b011 : excREnc_uid99_fpDivTest_q = 2'b00; + 3'b100 : excREnc_uid99_fpDivTest_q = 2'b11; + 3'b101 : excREnc_uid99_fpDivTest_q = 2'b00; + 3'b110 : excREnc_uid99_fpDivTest_q = 2'b00; + 3'b111 : excREnc_uid99_fpDivTest_q = 2'b00; + default : begin + // unreachable + excREnc_uid99_fpDivTest_q = 2'bxx; + end + endcase + // End reserved scope level + end + + // expRPostExc_uid107_fpDivTest(MUX,106)@16 + assign expRPostExc_uid107_fpDivTest_s = excREnc_uid99_fpDivTest_q; + always @(expRPostExc_uid107_fpDivTest_s or en or cstAllZWE_uid20_fpDivTest_q or redist2_excRPreExc_uid79_fpDivTest_b_1_q or cstAllOWE_uid18_fpDivTest_q) + begin + unique case (expRPostExc_uid107_fpDivTest_s) + 2'b00 : expRPostExc_uid107_fpDivTest_q = cstAllZWE_uid20_fpDivTest_q; + 2'b01 : expRPostExc_uid107_fpDivTest_q = redist2_excRPreExc_uid79_fpDivTest_b_1_q; + 2'b10 : expRPostExc_uid107_fpDivTest_q = cstAllOWE_uid18_fpDivTest_q; + 2'b11 : expRPostExc_uid107_fpDivTest_q = cstAllOWE_uid18_fpDivTest_q; + default : expRPostExc_uid107_fpDivTest_q = 8'b0; + endcase + end + + // oneFracRPostExc2_uid100_fpDivTest(CONSTANT,99) + assign oneFracRPostExc2_uid100_fpDivTest_q = 23'b00000000000000000000001; + + // fracRPreExc_uid78_fpDivTest(BITSELECT,77)@15 + assign fracRPreExc_uid78_fpDivTest_in = expFracPostRnd_uid76_fpDivTest_q[23:0]; + assign fracRPreExc_uid78_fpDivTest_b = fracRPreExc_uid78_fpDivTest_in[23:1]; + + // redist3_fracRPreExc_uid78_fpDivTest_b_1(DELAY,155) + dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) + redist3_fracRPreExc_uid78_fpDivTest_b_1 ( .xin(fracRPreExc_uid78_fpDivTest_b), .xout(redist3_fracRPreExc_uid78_fpDivTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // fracRPostExc_uid103_fpDivTest(MUX,102)@16 + assign fracRPostExc_uid103_fpDivTest_s = excREnc_uid99_fpDivTest_q; + always @(fracRPostExc_uid103_fpDivTest_s or en or paddingY_uid15_fpDivTest_q or redist3_fracRPreExc_uid78_fpDivTest_b_1_q or oneFracRPostExc2_uid100_fpDivTest_q) + begin + unique case (fracRPostExc_uid103_fpDivTest_s) + 2'b00 : fracRPostExc_uid103_fpDivTest_q = paddingY_uid15_fpDivTest_q; + 2'b01 : fracRPostExc_uid103_fpDivTest_q = redist3_fracRPreExc_uid78_fpDivTest_b_1_q; + 2'b10 : fracRPostExc_uid103_fpDivTest_q = paddingY_uid15_fpDivTest_q; + 2'b11 : fracRPostExc_uid103_fpDivTest_q = oneFracRPostExc2_uid100_fpDivTest_q; + default : fracRPostExc_uid103_fpDivTest_q = 23'b0; + endcase + end + + // divR_uid110_fpDivTest(BITJOIN,109)@16 + assign divR_uid110_fpDivTest_q = {sRPostExc_uid109_fpDivTest_q, expRPostExc_uid107_fpDivTest_q, fracRPostExc_uid103_fpDivTest_q}; + + // xOut(GPOUT,4)@16 + assign q = divR_uid110_fpDivTest_q; + +endmodule diff --git a/hw/rtl/fp_cores/altera/acl_fp_div_memoryC0_uid112_invTables_lutmem.hex b/hw/rtl/fp_cores/altera/acl_fp_div_memoryC0_uid112_invTables_lutmem.hex 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+:0201E800011400 +:0201E9000114FF +:0201EA00011002 +:0201EB00011100 +:0201EC00010F01 +:0201ED00010E01 +:0201EE00010D01 +:0201EF00010C01 +:0201F000010B01 +:0201F100010902 +:0201F200010BFF +:0201F300010801 +:0201F400010800 +:0201F500010601 +:0201F600010600 +:0201F7000107FE +:0201F8000105FF +:0201F900010300 +:0201FA00010200 +:0201FB000102FF +:0201FC000103FD +:0201FD000102FD +:0201FE000100FE +:0201FF000100FD +:00000001ff diff --git a/hw/rtl/fp_cores/altera/acl_fp_ftoi.sv b/hw/rtl/fp_cores/altera/acl_fp_ftoi.sv new file mode 100644 index 00000000..ccb8326c --- /dev/null +++ b/hw/rtl/fp_cores/altera/acl_fp_ftoi.sv @@ -0,0 +1,518 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_fp_ftoi +// SystemVerilog created on Wed Aug 5 12:58:15 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_fp_ftoi ( + input wire [31:0] a, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire [0:0] GND_q; + wire [7:0] cstAllOWE_uid6_fpToFxPTest_q; + wire [22:0] cstZeroWF_uid7_fpToFxPTest_q; + wire [7:0] cstAllZWE_uid8_fpToFxPTest_q; + wire [7:0] exp_x_uid9_fpToFxPTest_b; + wire [22:0] frac_x_uid10_fpToFxPTest_b; + wire [0:0] excZ_x_uid11_fpToFxPTest_qi; + reg [0:0] excZ_x_uid11_fpToFxPTest_q; + wire [0:0] expXIsMax_uid12_fpToFxPTest_qi; + reg [0:0] expXIsMax_uid12_fpToFxPTest_q; + wire [0:0] fracXIsZero_uid13_fpToFxPTest_qi; + reg [0:0] fracXIsZero_uid13_fpToFxPTest_q; + wire [0:0] fracXIsNotZero_uid14_fpToFxPTest_q; + wire [0:0] excI_x_uid15_fpToFxPTest_q; + wire [0:0] excN_x_uid16_fpToFxPTest_q; + wire [0:0] invExcXZ_uid22_fpToFxPTest_q; + wire [23:0] oFracX_uid23_fpToFxPTest_q; + wire [0:0] signX_uid25_fpToFxPTest_b; + wire [8:0] ovfExpVal_uid26_fpToFxPTest_q; + wire [10:0] ovfExpRange_uid27_fpToFxPTest_a; + wire [10:0] ovfExpRange_uid27_fpToFxPTest_b; + logic [10:0] ovfExpRange_uid27_fpToFxPTest_o; + wire [0:0] ovfExpRange_uid27_fpToFxPTest_n; + wire [7:0] udfExpVal_uid28_fpToFxPTest_q; + wire [10:0] udf_uid29_fpToFxPTest_a; + wire [10:0] udf_uid29_fpToFxPTest_b; + logic [10:0] udf_uid29_fpToFxPTest_o; + wire [0:0] udf_uid29_fpToFxPTest_n; + wire [8:0] ovfExpVal_uid30_fpToFxPTest_q; + wire [10:0] shiftValE_uid31_fpToFxPTest_a; + wire [10:0] shiftValE_uid31_fpToFxPTest_b; + logic [10:0] shiftValE_uid31_fpToFxPTest_o; + wire [9:0] shiftValE_uid31_fpToFxPTest_q; + wire [5:0] shiftValRaw_uid32_fpToFxPTest_in; + wire [5:0] shiftValRaw_uid32_fpToFxPTest_b; + wire [5:0] maxShiftCst_uid33_fpToFxPTest_q; + wire [11:0] shiftOutOfRange_uid34_fpToFxPTest_a; + wire [11:0] shiftOutOfRange_uid34_fpToFxPTest_b; + logic [11:0] shiftOutOfRange_uid34_fpToFxPTest_o; + wire [0:0] shiftOutOfRange_uid34_fpToFxPTest_n; + wire [0:0] shiftVal_uid35_fpToFxPTest_s; + reg [5:0] shiftVal_uid35_fpToFxPTest_q; + wire [31:0] shifterIn_uid37_fpToFxPTest_q; + wire [31:0] maxPosValueS_uid39_fpToFxPTest_q; + wire [31:0] maxNegValueS_uid40_fpToFxPTest_q; + wire [32:0] zRightShiferNoStickyOut_uid41_fpToFxPTest_q; + wire [32:0] xXorSignE_uid42_fpToFxPTest_b; + wire [32:0] xXorSignE_uid42_fpToFxPTest_q; + wire [2:0] d0_uid43_fpToFxPTest_q; + wire [33:0] sPostRndFull_uid44_fpToFxPTest_a; + wire [33:0] sPostRndFull_uid44_fpToFxPTest_b; + logic [33:0] sPostRndFull_uid44_fpToFxPTest_o; + wire [33:0] sPostRndFull_uid44_fpToFxPTest_q; + wire [32:0] sPostRnd_uid45_fpToFxPTest_in; + wire [31:0] sPostRnd_uid45_fpToFxPTest_b; + wire [34:0] sPostRnd_uid46_fpToFxPTest_in; + wire [33:0] sPostRnd_uid46_fpToFxPTest_b; + wire [35:0] rndOvfPos_uid47_fpToFxPTest_a; + wire [35:0] rndOvfPos_uid47_fpToFxPTest_b; + logic [35:0] rndOvfPos_uid47_fpToFxPTest_o; + wire [0:0] rndOvfPos_uid47_fpToFxPTest_c; + wire [0:0] ovfPostRnd_uid48_fpToFxPTest_qi; + reg [0:0] ovfPostRnd_uid48_fpToFxPTest_q; + wire [2:0] muxSelConc_uid49_fpToFxPTest_q; + reg [1:0] muxSel_uid50_fpToFxPTest_q; + wire [31:0] maxNegValueU_uid51_fpToFxPTest_q; + wire [1:0] finalOut_uid52_fpToFxPTest_s; + reg [31:0] finalOut_uid52_fpToFxPTest_q; + wire [15:0] rightShiftStage0Idx1Rng16_uid56_rightShiferNoStickyOut_uid38_fpToFxPTest_b; + wire [15:0] rightShiftStage0Idx1Pad16_uid57_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [31:0] rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [1:0] rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_s; + reg [31:0] rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [27:0] rightShiftStage1Idx1Rng4_uid63_rightShiferNoStickyOut_uid38_fpToFxPTest_b; + wire [3:0] rightShiftStage1Idx1Pad4_uid64_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [31:0] rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [23:0] rightShiftStage1Idx2Rng8_uid66_rightShiferNoStickyOut_uid38_fpToFxPTest_b; + wire [31:0] rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [19:0] rightShiftStage1Idx3Rng12_uid69_rightShiferNoStickyOut_uid38_fpToFxPTest_b; + wire [11:0] rightShiftStage1Idx3Pad12_uid70_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [31:0] rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [1:0] rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_s; + reg [31:0] rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [30:0] rightShiftStage2Idx1Rng1_uid74_rightShiferNoStickyOut_uid38_fpToFxPTest_b; + wire [31:0] rightShiftStage2Idx1_uid76_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [29:0] rightShiftStage2Idx2Rng2_uid77_rightShiferNoStickyOut_uid38_fpToFxPTest_b; + wire [1:0] rightShiftStage2Idx2Pad2_uid78_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [31:0] rightShiftStage2Idx2_uid79_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [28:0] rightShiftStage2Idx3Rng3_uid80_rightShiferNoStickyOut_uid38_fpToFxPTest_b; + wire [2:0] rightShiftStage2Idx3Pad3_uid81_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [31:0] rightShiftStage2Idx3_uid82_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [1:0] rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_s; + reg [31:0] rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + wire [1:0] rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_b; + wire [1:0] rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_c; + wire [1:0] rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_d; + reg [31:0] redist0_sPostRnd_uid45_fpToFxPTest_b_1_q; + reg [0:0] redist1_udf_uid29_fpToFxPTest_n_5_q; + reg [0:0] redist2_ovfExpRange_uid27_fpToFxPTest_n_4_q; + reg [0:0] redist3_signX_uid25_fpToFxPTest_b_3_q; + reg [0:0] redist4_signX_uid25_fpToFxPTest_b_5_q; + reg [0:0] redist5_fracXIsZero_uid13_fpToFxPTest_q_2_q; + reg [0:0] redist6_expXIsMax_uid12_fpToFxPTest_q_4_q; + reg [0:0] redist7_excZ_x_uid11_fpToFxPTest_q_2_q; + reg [22:0] redist8_frac_x_uid10_fpToFxPTest_b_2_q; + + + // maxNegValueU_uid51_fpToFxPTest(CONSTANT,50) + assign maxNegValueU_uid51_fpToFxPTest_q = 32'b00000000000000000000000000000000; + + // maxNegValueS_uid40_fpToFxPTest(CONSTANT,39) + assign maxNegValueS_uid40_fpToFxPTest_q = 32'b10000000000000000000000000000000; + + // maxPosValueS_uid39_fpToFxPTest(CONSTANT,38) + assign maxPosValueS_uid39_fpToFxPTest_q = 32'b01111111111111111111111111111111; + + // d0_uid43_fpToFxPTest(CONSTANT,42) + assign d0_uid43_fpToFxPTest_q = 3'b001; + + // signX_uid25_fpToFxPTest(BITSELECT,24)@0 + assign signX_uid25_fpToFxPTest_b = a[31:31]; + + // redist3_signX_uid25_fpToFxPTest_b_3(DELAY,89) + dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") ) + redist3_signX_uid25_fpToFxPTest_b_3 ( .xin(signX_uid25_fpToFxPTest_b), .xout(redist3_signX_uid25_fpToFxPTest_b_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // GND(CONSTANT,0) + assign GND_q = 1'b0; + + // rightShiftStage2Idx3Pad3_uid81_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,80) + assign rightShiftStage2Idx3Pad3_uid81_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 3'b000; + + // rightShiftStage2Idx3Rng3_uid80_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,79)@2 + assign rightShiftStage2Idx3Rng3_uid80_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:3]; + + // rightShiftStage2Idx3_uid82_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,81)@2 + assign rightShiftStage2Idx3_uid82_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage2Idx3Pad3_uid81_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage2Idx3Rng3_uid80_rightShiferNoStickyOut_uid38_fpToFxPTest_b}; + + // rightShiftStage2Idx2Pad2_uid78_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,77) + assign rightShiftStage2Idx2Pad2_uid78_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 2'b00; + + // rightShiftStage2Idx2Rng2_uid77_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,76)@2 + assign rightShiftStage2Idx2Rng2_uid77_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:2]; + + // rightShiftStage2Idx2_uid79_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,78)@2 + assign rightShiftStage2Idx2_uid79_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage2Idx2Pad2_uid78_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage2Idx2Rng2_uid77_rightShiferNoStickyOut_uid38_fpToFxPTest_b}; + + // rightShiftStage2Idx1Rng1_uid74_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,73)@2 + assign rightShiftStage2Idx1Rng1_uid74_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:1]; + + // rightShiftStage2Idx1_uid76_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,75)@2 + assign rightShiftStage2Idx1_uid76_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {GND_q, rightShiftStage2Idx1Rng1_uid74_rightShiferNoStickyOut_uid38_fpToFxPTest_b}; + + // rightShiftStage1Idx3Pad12_uid70_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,69) + assign rightShiftStage1Idx3Pad12_uid70_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 12'b000000000000; + + // rightShiftStage1Idx3Rng12_uid69_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,68)@2 + assign rightShiftStage1Idx3Rng12_uid69_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:12]; + + // rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,70)@2 + assign rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage1Idx3Pad12_uid70_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage1Idx3Rng12_uid69_rightShiferNoStickyOut_uid38_fpToFxPTest_b}; + + // cstAllZWE_uid8_fpToFxPTest(CONSTANT,7) + assign cstAllZWE_uid8_fpToFxPTest_q = 8'b00000000; + + // rightShiftStage1Idx2Rng8_uid66_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,65)@2 + assign rightShiftStage1Idx2Rng8_uid66_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:8]; + + // rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,67)@2 + assign rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {cstAllZWE_uid8_fpToFxPTest_q, rightShiftStage1Idx2Rng8_uid66_rightShiferNoStickyOut_uid38_fpToFxPTest_b}; + + // rightShiftStage1Idx1Pad4_uid64_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,63) + assign rightShiftStage1Idx1Pad4_uid64_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 4'b0000; + + // rightShiftStage1Idx1Rng4_uid63_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,62)@2 + assign rightShiftStage1Idx1Rng4_uid63_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:4]; + + // rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,64)@2 + assign rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage1Idx1Pad4_uid64_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage1Idx1Rng4_uid63_rightShiferNoStickyOut_uid38_fpToFxPTest_b}; + + // rightShiftStage0Idx1Pad16_uid57_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,56) + assign rightShiftStage0Idx1Pad16_uid57_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 16'b0000000000000000; + + // rightShiftStage0Idx1Rng16_uid56_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,55)@2 + assign rightShiftStage0Idx1Rng16_uid56_rightShiferNoStickyOut_uid38_fpToFxPTest_b = shifterIn_uid37_fpToFxPTest_q[31:16]; + + // rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,57)@2 + assign rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage0Idx1Pad16_uid57_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage0Idx1Rng16_uid56_rightShiferNoStickyOut_uid38_fpToFxPTest_b}; + + // exp_x_uid9_fpToFxPTest(BITSELECT,8)@0 + assign exp_x_uid9_fpToFxPTest_b = a[30:23]; + + // excZ_x_uid11_fpToFxPTest(LOGICAL,10)@0 + 1 + assign excZ_x_uid11_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllZWE_uid8_fpToFxPTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + excZ_x_uid11_fpToFxPTest_delay ( .xin(excZ_x_uid11_fpToFxPTest_qi), .xout(excZ_x_uid11_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist7_excZ_x_uid11_fpToFxPTest_q_2(DELAY,93) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist7_excZ_x_uid11_fpToFxPTest_q_2 ( .xin(excZ_x_uid11_fpToFxPTest_q), .xout(redist7_excZ_x_uid11_fpToFxPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // invExcXZ_uid22_fpToFxPTest(LOGICAL,21)@2 + assign invExcXZ_uid22_fpToFxPTest_q = ~ (redist7_excZ_x_uid11_fpToFxPTest_q_2_q); + + // frac_x_uid10_fpToFxPTest(BITSELECT,9)@0 + assign frac_x_uid10_fpToFxPTest_b = a[22:0]; + + // redist8_frac_x_uid10_fpToFxPTest_b_2(DELAY,94) + dspba_delay_ver #( .width(23), .depth(2), .reset_kind("ASYNC") ) + redist8_frac_x_uid10_fpToFxPTest_b_2 ( .xin(frac_x_uid10_fpToFxPTest_b), .xout(redist8_frac_x_uid10_fpToFxPTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // oFracX_uid23_fpToFxPTest(BITJOIN,22)@2 + assign oFracX_uid23_fpToFxPTest_q = {invExcXZ_uid22_fpToFxPTest_q, redist8_frac_x_uid10_fpToFxPTest_b_2_q}; + + // shifterIn_uid37_fpToFxPTest(BITJOIN,36)@2 + assign shifterIn_uid37_fpToFxPTest_q = {oFracX_uid23_fpToFxPTest_q, cstAllZWE_uid8_fpToFxPTest_q}; + + // rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest(MUX,61)@2 + assign rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_s = rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_b; + always @(rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_s or en or shifterIn_uid37_fpToFxPTest_q or rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest_q or maxNegValueU_uid51_fpToFxPTest_q) + begin + unique case (rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_s) + 2'b00 : rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q = shifterIn_uid37_fpToFxPTest_q; + 2'b01 : rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q = rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + 2'b10 : rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q = maxNegValueU_uid51_fpToFxPTest_q; + 2'b11 : rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q = maxNegValueU_uid51_fpToFxPTest_q; + default : rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 32'b0; + endcase + end + + // rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest(MUX,72)@2 + assign rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_s = rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_c; + always @(rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_s or en or rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q or rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest_q or rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest_q or rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest_q) + begin + unique case (rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_s) + 2'b00 : rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q = rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + 2'b01 : rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q = rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + 2'b10 : rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q = rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + 2'b11 : rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q = rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + default : rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 32'b0; + endcase + end + + // maxShiftCst_uid33_fpToFxPTest(CONSTANT,32) + assign maxShiftCst_uid33_fpToFxPTest_q = 6'b100000; + + // ovfExpVal_uid30_fpToFxPTest(CONSTANT,29) + assign ovfExpVal_uid30_fpToFxPTest_q = 9'b010011101; + + // shiftValE_uid31_fpToFxPTest(SUB,30)@0 + 1 + assign shiftValE_uid31_fpToFxPTest_a = {{2{ovfExpVal_uid30_fpToFxPTest_q[8]}}, ovfExpVal_uid30_fpToFxPTest_q}; + assign shiftValE_uid31_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + shiftValE_uid31_fpToFxPTest_o <= 11'b0; + end + else if (en == 1'b1) + begin + shiftValE_uid31_fpToFxPTest_o <= $signed(shiftValE_uid31_fpToFxPTest_a) - $signed(shiftValE_uid31_fpToFxPTest_b); + end + end + assign shiftValE_uid31_fpToFxPTest_q = shiftValE_uid31_fpToFxPTest_o[9:0]; + + // shiftValRaw_uid32_fpToFxPTest(BITSELECT,31)@1 + assign shiftValRaw_uid32_fpToFxPTest_in = shiftValE_uid31_fpToFxPTest_q[5:0]; + assign shiftValRaw_uid32_fpToFxPTest_b = shiftValRaw_uid32_fpToFxPTest_in[5:0]; + + // shiftOutOfRange_uid34_fpToFxPTest(COMPARE,33)@1 + assign shiftOutOfRange_uid34_fpToFxPTest_a = {{2{shiftValE_uid31_fpToFxPTest_q[9]}}, shiftValE_uid31_fpToFxPTest_q}; + assign shiftOutOfRange_uid34_fpToFxPTest_b = {6'b000000, maxShiftCst_uid33_fpToFxPTest_q}; + assign shiftOutOfRange_uid34_fpToFxPTest_o = $signed(shiftOutOfRange_uid34_fpToFxPTest_a) - $signed(shiftOutOfRange_uid34_fpToFxPTest_b); + assign shiftOutOfRange_uid34_fpToFxPTest_n[0] = ~ (shiftOutOfRange_uid34_fpToFxPTest_o[11]); + + // shiftVal_uid35_fpToFxPTest(MUX,34)@1 + 1 + assign shiftVal_uid35_fpToFxPTest_s = shiftOutOfRange_uid34_fpToFxPTest_n; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + shiftVal_uid35_fpToFxPTest_q <= 6'b0; + end + else if (en == 1'b1) + begin + unique case (shiftVal_uid35_fpToFxPTest_s) + 1'b0 : shiftVal_uid35_fpToFxPTest_q <= shiftValRaw_uid32_fpToFxPTest_b; + 1'b1 : shiftVal_uid35_fpToFxPTest_q <= maxShiftCst_uid33_fpToFxPTest_q; + default : shiftVal_uid35_fpToFxPTest_q <= 6'b0; + endcase + end + end + + // rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select(BITSELECT,85)@2 + assign rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_b = shiftVal_uid35_fpToFxPTest_q[5:4]; + assign rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_c = shiftVal_uid35_fpToFxPTest_q[3:2]; + assign rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_d = shiftVal_uid35_fpToFxPTest_q[1:0]; + + // rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest(MUX,83)@2 + 1 + assign rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_s = rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_d; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= 32'b0; + end + else if (en == 1'b1) + begin + unique case (rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_s) + 2'b00 : rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + 2'b01 : rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= rightShiftStage2Idx1_uid76_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + 2'b10 : rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= rightShiftStage2Idx2_uid79_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + 2'b11 : rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= rightShiftStage2Idx3_uid82_rightShiferNoStickyOut_uid38_fpToFxPTest_q; + default : rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q <= 32'b0; + endcase + end + end + + // zRightShiferNoStickyOut_uid41_fpToFxPTest(BITJOIN,40)@3 + assign zRightShiferNoStickyOut_uid41_fpToFxPTest_q = {GND_q, rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q}; + + // xXorSignE_uid42_fpToFxPTest(LOGICAL,41)@3 + assign xXorSignE_uid42_fpToFxPTest_b = {{32{redist3_signX_uid25_fpToFxPTest_b_3_q[0]}}, redist3_signX_uid25_fpToFxPTest_b_3_q}; + assign xXorSignE_uid42_fpToFxPTest_q = zRightShiferNoStickyOut_uid41_fpToFxPTest_q ^ xXorSignE_uid42_fpToFxPTest_b; + + // sPostRndFull_uid44_fpToFxPTest(ADD,43)@3 + 1 + assign sPostRndFull_uid44_fpToFxPTest_a = {{1{xXorSignE_uid42_fpToFxPTest_q[32]}}, xXorSignE_uid42_fpToFxPTest_q}; + assign sPostRndFull_uid44_fpToFxPTest_b = {{31{d0_uid43_fpToFxPTest_q[2]}}, d0_uid43_fpToFxPTest_q}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + sPostRndFull_uid44_fpToFxPTest_o <= 34'b0; + end + else if (en == 1'b1) + begin + sPostRndFull_uid44_fpToFxPTest_o <= $signed(sPostRndFull_uid44_fpToFxPTest_a) + $signed(sPostRndFull_uid44_fpToFxPTest_b); + end + end + assign sPostRndFull_uid44_fpToFxPTest_q = sPostRndFull_uid44_fpToFxPTest_o[33:0]; + + // sPostRnd_uid45_fpToFxPTest(BITSELECT,44)@4 + assign sPostRnd_uid45_fpToFxPTest_in = sPostRndFull_uid44_fpToFxPTest_q[32:0]; + assign sPostRnd_uid45_fpToFxPTest_b = sPostRnd_uid45_fpToFxPTest_in[32:1]; + + // redist0_sPostRnd_uid45_fpToFxPTest_b_1(DELAY,86) + dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") ) + redist0_sPostRnd_uid45_fpToFxPTest_b_1 ( .xin(sPostRnd_uid45_fpToFxPTest_b), .xout(redist0_sPostRnd_uid45_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist4_signX_uid25_fpToFxPTest_b_5(DELAY,90) + dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") ) + redist4_signX_uid25_fpToFxPTest_b_5 ( .xin(redist3_signX_uid25_fpToFxPTest_b_3_q), .xout(redist4_signX_uid25_fpToFxPTest_b_5_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // udfExpVal_uid28_fpToFxPTest(CONSTANT,27) + assign udfExpVal_uid28_fpToFxPTest_q = 8'b01111101; + + // udf_uid29_fpToFxPTest(COMPARE,28)@0 + 1 + assign udf_uid29_fpToFxPTest_a = {{3{udfExpVal_uid28_fpToFxPTest_q[7]}}, udfExpVal_uid28_fpToFxPTest_q}; + assign udf_uid29_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + udf_uid29_fpToFxPTest_o <= 11'b0; + end + else if (en == 1'b1) + begin + udf_uid29_fpToFxPTest_o <= $signed(udf_uid29_fpToFxPTest_a) - $signed(udf_uid29_fpToFxPTest_b); + end + end + assign udf_uid29_fpToFxPTest_n[0] = ~ (udf_uid29_fpToFxPTest_o[10]); + + // redist1_udf_uid29_fpToFxPTest_n_5(DELAY,87) + dspba_delay_ver #( .width(1), .depth(4), .reset_kind("ASYNC") ) + redist1_udf_uid29_fpToFxPTest_n_5 ( .xin(udf_uid29_fpToFxPTest_n), .xout(redist1_udf_uid29_fpToFxPTest_n_5_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // sPostRnd_uid46_fpToFxPTest(BITSELECT,45)@4 + assign sPostRnd_uid46_fpToFxPTest_in = {{1{sPostRndFull_uid44_fpToFxPTest_q[33]}}, sPostRndFull_uid44_fpToFxPTest_q}; + assign sPostRnd_uid46_fpToFxPTest_b = sPostRnd_uid46_fpToFxPTest_in[34:1]; + + // rndOvfPos_uid47_fpToFxPTest(COMPARE,46)@4 + assign rndOvfPos_uid47_fpToFxPTest_a = {4'b0000, maxPosValueS_uid39_fpToFxPTest_q}; + assign rndOvfPos_uid47_fpToFxPTest_b = {{2{sPostRnd_uid46_fpToFxPTest_b[33]}}, sPostRnd_uid46_fpToFxPTest_b}; + assign rndOvfPos_uid47_fpToFxPTest_o = $signed(rndOvfPos_uid47_fpToFxPTest_a) - $signed(rndOvfPos_uid47_fpToFxPTest_b); + assign rndOvfPos_uid47_fpToFxPTest_c[0] = rndOvfPos_uid47_fpToFxPTest_o[35]; + + // ovfExpVal_uid26_fpToFxPTest(CONSTANT,25) + assign ovfExpVal_uid26_fpToFxPTest_q = 9'b010011110; + + // ovfExpRange_uid27_fpToFxPTest(COMPARE,26)@0 + 1 + assign ovfExpRange_uid27_fpToFxPTest_a = {3'b000, exp_x_uid9_fpToFxPTest_b}; + assign ovfExpRange_uid27_fpToFxPTest_b = {{2{ovfExpVal_uid26_fpToFxPTest_q[8]}}, ovfExpVal_uid26_fpToFxPTest_q}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + ovfExpRange_uid27_fpToFxPTest_o <= 11'b0; + end + else if (en == 1'b1) + begin + ovfExpRange_uid27_fpToFxPTest_o <= $signed(ovfExpRange_uid27_fpToFxPTest_a) - $signed(ovfExpRange_uid27_fpToFxPTest_b); + end + end + assign ovfExpRange_uid27_fpToFxPTest_n[0] = ~ (ovfExpRange_uid27_fpToFxPTest_o[10]); + + // redist2_ovfExpRange_uid27_fpToFxPTest_n_4(DELAY,88) + dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") ) + redist2_ovfExpRange_uid27_fpToFxPTest_n_4 ( .xin(ovfExpRange_uid27_fpToFxPTest_n), .xout(redist2_ovfExpRange_uid27_fpToFxPTest_n_4_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // cstZeroWF_uid7_fpToFxPTest(CONSTANT,6) + assign cstZeroWF_uid7_fpToFxPTest_q = 23'b00000000000000000000000; + + // fracXIsZero_uid13_fpToFxPTest(LOGICAL,12)@2 + 1 + assign fracXIsZero_uid13_fpToFxPTest_qi = cstZeroWF_uid7_fpToFxPTest_q == redist8_frac_x_uid10_fpToFxPTest_b_2_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + fracXIsZero_uid13_fpToFxPTest_delay ( .xin(fracXIsZero_uid13_fpToFxPTest_qi), .xout(fracXIsZero_uid13_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist5_fracXIsZero_uid13_fpToFxPTest_q_2(DELAY,91) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist5_fracXIsZero_uid13_fpToFxPTest_q_2 ( .xin(fracXIsZero_uid13_fpToFxPTest_q), .xout(redist5_fracXIsZero_uid13_fpToFxPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // cstAllOWE_uid6_fpToFxPTest(CONSTANT,5) + assign cstAllOWE_uid6_fpToFxPTest_q = 8'b11111111; + + // expXIsMax_uid12_fpToFxPTest(LOGICAL,11)@0 + 1 + assign expXIsMax_uid12_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllOWE_uid6_fpToFxPTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + expXIsMax_uid12_fpToFxPTest_delay ( .xin(expXIsMax_uid12_fpToFxPTest_qi), .xout(expXIsMax_uid12_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist6_expXIsMax_uid12_fpToFxPTest_q_4(DELAY,92) + dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") ) + redist6_expXIsMax_uid12_fpToFxPTest_q_4 ( .xin(expXIsMax_uid12_fpToFxPTest_q), .xout(redist6_expXIsMax_uid12_fpToFxPTest_q_4_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excI_x_uid15_fpToFxPTest(LOGICAL,14)@4 + assign excI_x_uid15_fpToFxPTest_q = redist6_expXIsMax_uid12_fpToFxPTest_q_4_q & redist5_fracXIsZero_uid13_fpToFxPTest_q_2_q; + + // fracXIsNotZero_uid14_fpToFxPTest(LOGICAL,13)@4 + assign fracXIsNotZero_uid14_fpToFxPTest_q = ~ (redist5_fracXIsZero_uid13_fpToFxPTest_q_2_q); + + // excN_x_uid16_fpToFxPTest(LOGICAL,15)@4 + assign excN_x_uid16_fpToFxPTest_q = redist6_expXIsMax_uid12_fpToFxPTest_q_4_q & fracXIsNotZero_uid14_fpToFxPTest_q; + + // ovfPostRnd_uid48_fpToFxPTest(LOGICAL,47)@4 + 1 + assign ovfPostRnd_uid48_fpToFxPTest_qi = excN_x_uid16_fpToFxPTest_q | excI_x_uid15_fpToFxPTest_q | redist2_ovfExpRange_uid27_fpToFxPTest_n_4_q | rndOvfPos_uid47_fpToFxPTest_c; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + ovfPostRnd_uid48_fpToFxPTest_delay ( .xin(ovfPostRnd_uid48_fpToFxPTest_qi), .xout(ovfPostRnd_uid48_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // muxSelConc_uid49_fpToFxPTest(BITJOIN,48)@5 + assign muxSelConc_uid49_fpToFxPTest_q = {redist4_signX_uid25_fpToFxPTest_b_5_q, redist1_udf_uid29_fpToFxPTest_n_5_q, ovfPostRnd_uid48_fpToFxPTest_q}; + + // muxSel_uid50_fpToFxPTest(LOOKUP,49)@5 + always @(muxSelConc_uid49_fpToFxPTest_q) + begin + // Begin reserved scope level + unique case (muxSelConc_uid49_fpToFxPTest_q) + 3'b000 : muxSel_uid50_fpToFxPTest_q = 2'b00; + 3'b001 : muxSel_uid50_fpToFxPTest_q = 2'b01; + 3'b010 : muxSel_uid50_fpToFxPTest_q = 2'b11; + 3'b011 : muxSel_uid50_fpToFxPTest_q = 2'b11; + 3'b100 : muxSel_uid50_fpToFxPTest_q = 2'b00; + 3'b101 : muxSel_uid50_fpToFxPTest_q = 2'b10; + 3'b110 : muxSel_uid50_fpToFxPTest_q = 2'b11; + 3'b111 : muxSel_uid50_fpToFxPTest_q = 2'b11; + default : begin + // unreachable + muxSel_uid50_fpToFxPTest_q = 2'bxx; + end + endcase + // End reserved scope level + end + + // finalOut_uid52_fpToFxPTest(MUX,51)@5 + assign finalOut_uid52_fpToFxPTest_s = muxSel_uid50_fpToFxPTest_q; + always @(finalOut_uid52_fpToFxPTest_s or en or redist0_sPostRnd_uid45_fpToFxPTest_b_1_q or maxPosValueS_uid39_fpToFxPTest_q or maxNegValueS_uid40_fpToFxPTest_q or maxNegValueU_uid51_fpToFxPTest_q) + begin + unique case (finalOut_uid52_fpToFxPTest_s) + 2'b00 : finalOut_uid52_fpToFxPTest_q = redist0_sPostRnd_uid45_fpToFxPTest_b_1_q; + 2'b01 : finalOut_uid52_fpToFxPTest_q = maxPosValueS_uid39_fpToFxPTest_q; + 2'b10 : finalOut_uid52_fpToFxPTest_q = maxNegValueS_uid40_fpToFxPTest_q; + 2'b11 : finalOut_uid52_fpToFxPTest_q = maxNegValueU_uid51_fpToFxPTest_q; + default : finalOut_uid52_fpToFxPTest_q = 32'b0; + endcase + end + + // xOut(GPOUT,4)@5 + assign q = finalOut_uid52_fpToFxPTest_q; + +endmodule diff --git a/hw/rtl/fp_cores/altera/acl_fp_ftou.sv b/hw/rtl/fp_cores/altera/acl_fp_ftou.sv new file mode 100644 index 00000000..06a67a6a --- /dev/null +++ b/hw/rtl/fp_cores/altera/acl_fp_ftou.sv @@ -0,0 +1,503 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_fp_ftou +// SystemVerilog created on Wed Aug 5 12:58:15 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_fp_ftou ( + input wire [31:0] a, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire [0:0] GND_q; + wire [0:0] VCC_q; + wire [7:0] cstAllOWE_uid6_fpToFxPTest_q; + wire [22:0] cstZeroWF_uid7_fpToFxPTest_q; + wire [7:0] cstAllZWE_uid8_fpToFxPTest_q; + wire [7:0] exp_x_uid9_fpToFxPTest_b; + wire [22:0] frac_x_uid10_fpToFxPTest_b; + wire [0:0] excZ_x_uid11_fpToFxPTest_qi; + reg [0:0] excZ_x_uid11_fpToFxPTest_q; + wire [0:0] expXIsMax_uid12_fpToFxPTest_qi; + reg [0:0] expXIsMax_uid12_fpToFxPTest_q; + wire [0:0] fracXIsZero_uid13_fpToFxPTest_qi; + reg [0:0] fracXIsZero_uid13_fpToFxPTest_q; + wire [0:0] fracXIsNotZero_uid14_fpToFxPTest_q; + wire [0:0] excI_x_uid15_fpToFxPTest_q; + wire [0:0] excN_x_uid16_fpToFxPTest_q; + wire [0:0] invExcXZ_uid22_fpToFxPTest_q; + wire [23:0] oFracX_uid23_fpToFxPTest_q; + wire [0:0] signX_uid25_fpToFxPTest_b; + wire [8:0] ovfExpVal_uid26_fpToFxPTest_q; + wire [10:0] ovf_uid27_fpToFxPTest_a; + wire [10:0] ovf_uid27_fpToFxPTest_b; + logic [10:0] ovf_uid27_fpToFxPTest_o; + wire [0:0] ovf_uid27_fpToFxPTest_n; + wire [0:0] negOrOvf_uid28_fpToFxPTest_q; + wire [7:0] udfExpVal_uid29_fpToFxPTest_q; + wire [10:0] udf_uid30_fpToFxPTest_a; + wire [10:0] udf_uid30_fpToFxPTest_b; + logic [10:0] udf_uid30_fpToFxPTest_o; + wire [0:0] udf_uid30_fpToFxPTest_n; + wire [8:0] ovfExpVal_uid31_fpToFxPTest_q; + wire [10:0] shiftValE_uid32_fpToFxPTest_a; + wire [10:0] shiftValE_uid32_fpToFxPTest_b; + logic [10:0] shiftValE_uid32_fpToFxPTest_o; + wire [9:0] shiftValE_uid32_fpToFxPTest_q; + wire [5:0] shiftValRaw_uid33_fpToFxPTest_in; + wire [5:0] shiftValRaw_uid33_fpToFxPTest_b; + wire [5:0] maxShiftCst_uid34_fpToFxPTest_q; + wire [11:0] shiftOutOfRange_uid35_fpToFxPTest_a; + wire [11:0] shiftOutOfRange_uid35_fpToFxPTest_b; + logic [11:0] shiftOutOfRange_uid35_fpToFxPTest_o; + wire [0:0] shiftOutOfRange_uid35_fpToFxPTest_n; + wire [0:0] shiftVal_uid36_fpToFxPTest_s; + reg [5:0] shiftVal_uid36_fpToFxPTest_q; + wire [8:0] zPadd_uid37_fpToFxPTest_q; + wire [32:0] shifterIn_uid38_fpToFxPTest_q; + wire [31:0] maxPosValueU_uid40_fpToFxPTest_q; + wire [31:0] maxNegValueU_uid41_fpToFxPTest_q; + wire [33:0] zRightShiferNoStickyOut_uid43_fpToFxPTest_q; + wire [34:0] sPostRndFull_uid44_fpToFxPTest_a; + wire [34:0] sPostRndFull_uid44_fpToFxPTest_b; + logic [34:0] sPostRndFull_uid44_fpToFxPTest_o; + wire [34:0] sPostRndFull_uid44_fpToFxPTest_q; + wire [32:0] sPostRnd_uid45_fpToFxPTest_in; + wire [31:0] sPostRnd_uid45_fpToFxPTest_b; + wire [33:0] sPostRndFullMSBU_uid46_fpToFxPTest_in; + wire [0:0] sPostRndFullMSBU_uid46_fpToFxPTest_b; + wire [0:0] ovfPostRnd_uid47_fpToFxPTest_qi; + reg [0:0] ovfPostRnd_uid47_fpToFxPTest_q; + wire [2:0] muxSelConc_uid48_fpToFxPTest_q; + reg [1:0] muxSel_uid49_fpToFxPTest_q; + wire [1:0] finalOut_uid51_fpToFxPTest_s; + reg [31:0] finalOut_uid51_fpToFxPTest_q; + wire [16:0] rightShiftStage0Idx1Rng16_uid55_rightShiferNoStickyOut_uid39_fpToFxPTest_b; + wire [15:0] rightShiftStage0Idx1Pad16_uid56_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [32:0] rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [0:0] rightShiftStage0Idx2Rng32_uid58_rightShiferNoStickyOut_uid39_fpToFxPTest_b; + wire [32:0] rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [32:0] rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [1:0] rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_s; + reg [32:0] rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [28:0] rightShiftStage1Idx1Rng4_uid64_rightShiferNoStickyOut_uid39_fpToFxPTest_b; + wire [3:0] rightShiftStage1Idx1Pad4_uid65_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [32:0] rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [24:0] rightShiftStage1Idx2Rng8_uid67_rightShiferNoStickyOut_uid39_fpToFxPTest_b; + wire [32:0] rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [20:0] rightShiftStage1Idx3Rng12_uid70_rightShiferNoStickyOut_uid39_fpToFxPTest_b; + wire [11:0] rightShiftStage1Idx3Pad12_uid71_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [32:0] rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [1:0] rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_s; + reg [32:0] rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [31:0] rightShiftStage2Idx1Rng1_uid75_rightShiferNoStickyOut_uid39_fpToFxPTest_b; + wire [32:0] rightShiftStage2Idx1_uid77_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [30:0] rightShiftStage2Idx2Rng2_uid78_rightShiferNoStickyOut_uid39_fpToFxPTest_b; + wire [1:0] rightShiftStage2Idx2Pad2_uid79_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [32:0] rightShiftStage2Idx2_uid80_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [29:0] rightShiftStage2Idx3Rng3_uid81_rightShiferNoStickyOut_uid39_fpToFxPTest_b; + wire [2:0] rightShiftStage2Idx3Pad3_uid82_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [32:0] rightShiftStage2Idx3_uid83_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [1:0] rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_s; + reg [32:0] rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + wire [1:0] rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_b; + wire [1:0] rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_c; + wire [1:0] rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_d; + reg [31:0] redist0_sPostRnd_uid45_fpToFxPTest_b_1_q; + reg [0:0] redist1_udf_uid30_fpToFxPTest_n_4_q; + reg [0:0] redist2_ovf_uid27_fpToFxPTest_n_3_q; + reg [0:0] redist3_signX_uid25_fpToFxPTest_b_3_q; + reg [0:0] redist4_signX_uid25_fpToFxPTest_b_4_q; + reg [0:0] redist5_expXIsMax_uid12_fpToFxPTest_q_3_q; + reg [0:0] redist6_excZ_x_uid11_fpToFxPTest_q_2_q; + reg [22:0] redist7_frac_x_uid10_fpToFxPTest_b_2_q; + + + // maxNegValueU_uid41_fpToFxPTest(CONSTANT,40) + assign maxNegValueU_uid41_fpToFxPTest_q = 32'b00000000000000000000000000000000; + + // maxPosValueU_uid40_fpToFxPTest(CONSTANT,39) + assign maxPosValueU_uid40_fpToFxPTest_q = 32'b11111111111111111111111111111111; + + // VCC(CONSTANT,1) + assign VCC_q = 1'b1; + + // GND(CONSTANT,0) + assign GND_q = 1'b0; + + // rightShiftStage2Idx3Pad3_uid82_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,81) + assign rightShiftStage2Idx3Pad3_uid82_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 3'b000; + + // rightShiftStage2Idx3Rng3_uid81_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,80)@2 + assign rightShiftStage2Idx3Rng3_uid81_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:3]; + + // rightShiftStage2Idx3_uid83_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,82)@2 + assign rightShiftStage2Idx3_uid83_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage2Idx3Pad3_uid82_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage2Idx3Rng3_uid81_rightShiferNoStickyOut_uid39_fpToFxPTest_b}; + + // rightShiftStage2Idx2Pad2_uid79_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,78) + assign rightShiftStage2Idx2Pad2_uid79_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 2'b00; + + // rightShiftStage2Idx2Rng2_uid78_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,77)@2 + assign rightShiftStage2Idx2Rng2_uid78_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:2]; + + // rightShiftStage2Idx2_uid80_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,79)@2 + assign rightShiftStage2Idx2_uid80_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage2Idx2Pad2_uid79_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage2Idx2Rng2_uid78_rightShiferNoStickyOut_uid39_fpToFxPTest_b}; + + // rightShiftStage2Idx1Rng1_uid75_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,74)@2 + assign rightShiftStage2Idx1Rng1_uid75_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:1]; + + // rightShiftStage2Idx1_uid77_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,76)@2 + assign rightShiftStage2Idx1_uid77_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {GND_q, rightShiftStage2Idx1Rng1_uid75_rightShiferNoStickyOut_uid39_fpToFxPTest_b}; + + // rightShiftStage1Idx3Pad12_uid71_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,70) + assign rightShiftStage1Idx3Pad12_uid71_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 12'b000000000000; + + // rightShiftStage1Idx3Rng12_uid70_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,69)@2 + assign rightShiftStage1Idx3Rng12_uid70_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:12]; + + // rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,71)@2 + assign rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage1Idx3Pad12_uid71_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage1Idx3Rng12_uid70_rightShiferNoStickyOut_uid39_fpToFxPTest_b}; + + // cstAllZWE_uid8_fpToFxPTest(CONSTANT,7) + assign cstAllZWE_uid8_fpToFxPTest_q = 8'b00000000; + + // rightShiftStage1Idx2Rng8_uid67_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,66)@2 + assign rightShiftStage1Idx2Rng8_uid67_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:8]; + + // rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,68)@2 + assign rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {cstAllZWE_uid8_fpToFxPTest_q, rightShiftStage1Idx2Rng8_uid67_rightShiferNoStickyOut_uid39_fpToFxPTest_b}; + + // rightShiftStage1Idx1Pad4_uid65_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,64) + assign rightShiftStage1Idx1Pad4_uid65_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 4'b0000; + + // rightShiftStage1Idx1Rng4_uid64_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,63)@2 + assign rightShiftStage1Idx1Rng4_uid64_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:4]; + + // rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,65)@2 + assign rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage1Idx1Pad4_uid65_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage1Idx1Rng4_uid64_rightShiferNoStickyOut_uid39_fpToFxPTest_b}; + + // rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,60) + assign rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 33'b000000000000000000000000000000000; + + // rightShiftStage0Idx2Rng32_uid58_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,57)@2 + assign rightShiftStage0Idx2Rng32_uid58_rightShiferNoStickyOut_uid39_fpToFxPTest_b = shifterIn_uid38_fpToFxPTest_q[32:32]; + + // rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,59)@2 + assign rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {maxNegValueU_uid41_fpToFxPTest_q, rightShiftStage0Idx2Rng32_uid58_rightShiferNoStickyOut_uid39_fpToFxPTest_b}; + + // rightShiftStage0Idx1Pad16_uid56_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,55) + assign rightShiftStage0Idx1Pad16_uid56_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 16'b0000000000000000; + + // rightShiftStage0Idx1Rng16_uid55_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,54)@2 + assign rightShiftStage0Idx1Rng16_uid55_rightShiferNoStickyOut_uid39_fpToFxPTest_b = shifterIn_uid38_fpToFxPTest_q[32:16]; + + // rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,56)@2 + assign rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage0Idx1Pad16_uid56_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage0Idx1Rng16_uid55_rightShiferNoStickyOut_uid39_fpToFxPTest_b}; + + // exp_x_uid9_fpToFxPTest(BITSELECT,8)@0 + assign exp_x_uid9_fpToFxPTest_b = a[30:23]; + + // excZ_x_uid11_fpToFxPTest(LOGICAL,10)@0 + 1 + assign excZ_x_uid11_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllZWE_uid8_fpToFxPTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + excZ_x_uid11_fpToFxPTest_delay ( .xin(excZ_x_uid11_fpToFxPTest_qi), .xout(excZ_x_uid11_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist6_excZ_x_uid11_fpToFxPTest_q_2(DELAY,93) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist6_excZ_x_uid11_fpToFxPTest_q_2 ( .xin(excZ_x_uid11_fpToFxPTest_q), .xout(redist6_excZ_x_uid11_fpToFxPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // invExcXZ_uid22_fpToFxPTest(LOGICAL,21)@2 + assign invExcXZ_uid22_fpToFxPTest_q = ~ (redist6_excZ_x_uid11_fpToFxPTest_q_2_q); + + // frac_x_uid10_fpToFxPTest(BITSELECT,9)@0 + assign frac_x_uid10_fpToFxPTest_b = a[22:0]; + + // redist7_frac_x_uid10_fpToFxPTest_b_2(DELAY,94) + dspba_delay_ver #( .width(23), .depth(2), .reset_kind("ASYNC") ) + redist7_frac_x_uid10_fpToFxPTest_b_2 ( .xin(frac_x_uid10_fpToFxPTest_b), .xout(redist7_frac_x_uid10_fpToFxPTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // oFracX_uid23_fpToFxPTest(BITJOIN,22)@2 + assign oFracX_uid23_fpToFxPTest_q = {invExcXZ_uid22_fpToFxPTest_q, redist7_frac_x_uid10_fpToFxPTest_b_2_q}; + + // zPadd_uid37_fpToFxPTest(CONSTANT,36) + assign zPadd_uid37_fpToFxPTest_q = 9'b000000000; + + // shifterIn_uid38_fpToFxPTest(BITJOIN,37)@2 + assign shifterIn_uid38_fpToFxPTest_q = {oFracX_uid23_fpToFxPTest_q, zPadd_uid37_fpToFxPTest_q}; + + // rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest(MUX,62)@2 + assign rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_s = rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_b; + always @(rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_s or en or shifterIn_uid38_fpToFxPTest_q or rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest_q) + begin + unique case (rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_s) + 2'b00 : rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q = shifterIn_uid38_fpToFxPTest_q; + 2'b01 : rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + 2'b10 : rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + 2'b11 : rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + default : rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 33'b0; + endcase + end + + // rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest(MUX,73)@2 + assign rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_s = rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_c; + always @(rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_s or en or rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest_q) + begin + unique case (rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_s) + 2'b00 : rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + 2'b01 : rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + 2'b10 : rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + 2'b11 : rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q = rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + default : rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 33'b0; + endcase + end + + // maxShiftCst_uid34_fpToFxPTest(CONSTANT,33) + assign maxShiftCst_uid34_fpToFxPTest_q = 6'b100001; + + // ovfExpVal_uid31_fpToFxPTest(CONSTANT,30) + assign ovfExpVal_uid31_fpToFxPTest_q = 9'b010011110; + + // shiftValE_uid32_fpToFxPTest(SUB,31)@0 + 1 + assign shiftValE_uid32_fpToFxPTest_a = {{2{ovfExpVal_uid31_fpToFxPTest_q[8]}}, ovfExpVal_uid31_fpToFxPTest_q}; + assign shiftValE_uid32_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + shiftValE_uid32_fpToFxPTest_o <= 11'b0; + end + else if (en == 1'b1) + begin + shiftValE_uid32_fpToFxPTest_o <= $signed(shiftValE_uid32_fpToFxPTest_a) - $signed(shiftValE_uid32_fpToFxPTest_b); + end + end + assign shiftValE_uid32_fpToFxPTest_q = shiftValE_uid32_fpToFxPTest_o[9:0]; + + // shiftValRaw_uid33_fpToFxPTest(BITSELECT,32)@1 + assign shiftValRaw_uid33_fpToFxPTest_in = shiftValE_uid32_fpToFxPTest_q[5:0]; + assign shiftValRaw_uid33_fpToFxPTest_b = shiftValRaw_uid33_fpToFxPTest_in[5:0]; + + // shiftOutOfRange_uid35_fpToFxPTest(COMPARE,34)@1 + assign shiftOutOfRange_uid35_fpToFxPTest_a = {{2{shiftValE_uid32_fpToFxPTest_q[9]}}, shiftValE_uid32_fpToFxPTest_q}; + assign shiftOutOfRange_uid35_fpToFxPTest_b = {6'b000000, maxShiftCst_uid34_fpToFxPTest_q}; + assign shiftOutOfRange_uid35_fpToFxPTest_o = $signed(shiftOutOfRange_uid35_fpToFxPTest_a) - $signed(shiftOutOfRange_uid35_fpToFxPTest_b); + assign shiftOutOfRange_uid35_fpToFxPTest_n[0] = ~ (shiftOutOfRange_uid35_fpToFxPTest_o[11]); + + // shiftVal_uid36_fpToFxPTest(MUX,35)@1 + 1 + assign shiftVal_uid36_fpToFxPTest_s = shiftOutOfRange_uid35_fpToFxPTest_n; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + shiftVal_uid36_fpToFxPTest_q <= 6'b0; + end + else if (en == 1'b1) + begin + unique case (shiftVal_uid36_fpToFxPTest_s) + 1'b0 : shiftVal_uid36_fpToFxPTest_q <= shiftValRaw_uid33_fpToFxPTest_b; + 1'b1 : shiftVal_uid36_fpToFxPTest_q <= maxShiftCst_uid34_fpToFxPTest_q; + default : shiftVal_uid36_fpToFxPTest_q <= 6'b0; + endcase + end + end + + // rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select(BITSELECT,86)@2 + assign rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_b = shiftVal_uid36_fpToFxPTest_q[5:4]; + assign rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_c = shiftVal_uid36_fpToFxPTest_q[3:2]; + assign rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_d = shiftVal_uid36_fpToFxPTest_q[1:0]; + + // rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest(MUX,84)@2 + 1 + assign rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_s = rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_d; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= 33'b0; + end + else if (en == 1'b1) + begin + unique case (rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_s) + 2'b00 : rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + 2'b01 : rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= rightShiftStage2Idx1_uid77_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + 2'b10 : rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= rightShiftStage2Idx2_uid80_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + 2'b11 : rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= rightShiftStage2Idx3_uid83_rightShiferNoStickyOut_uid39_fpToFxPTest_q; + default : rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q <= 33'b0; + endcase + end + end + + // zRightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,42)@3 + assign zRightShiferNoStickyOut_uid43_fpToFxPTest_q = {GND_q, rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q}; + + // sPostRndFull_uid44_fpToFxPTest(ADD,43)@3 + assign sPostRndFull_uid44_fpToFxPTest_a = {1'b0, zRightShiferNoStickyOut_uid43_fpToFxPTest_q}; + assign sPostRndFull_uid44_fpToFxPTest_b = {34'b0000000000000000000000000000000000, VCC_q}; + assign sPostRndFull_uid44_fpToFxPTest_o = $unsigned(sPostRndFull_uid44_fpToFxPTest_a) + $unsigned(sPostRndFull_uid44_fpToFxPTest_b); + assign sPostRndFull_uid44_fpToFxPTest_q = sPostRndFull_uid44_fpToFxPTest_o[34:0]; + + // sPostRnd_uid45_fpToFxPTest(BITSELECT,44)@3 + assign sPostRnd_uid45_fpToFxPTest_in = sPostRndFull_uid44_fpToFxPTest_q[32:0]; + assign sPostRnd_uid45_fpToFxPTest_b = sPostRnd_uid45_fpToFxPTest_in[32:1]; + + // redist0_sPostRnd_uid45_fpToFxPTest_b_1(DELAY,87) + dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") ) + redist0_sPostRnd_uid45_fpToFxPTest_b_1 ( .xin(sPostRnd_uid45_fpToFxPTest_b), .xout(redist0_sPostRnd_uid45_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // signX_uid25_fpToFxPTest(BITSELECT,24)@0 + assign signX_uid25_fpToFxPTest_b = a[31:31]; + + // redist3_signX_uid25_fpToFxPTest_b_3(DELAY,90) + dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") ) + redist3_signX_uid25_fpToFxPTest_b_3 ( .xin(signX_uid25_fpToFxPTest_b), .xout(redist3_signX_uid25_fpToFxPTest_b_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist4_signX_uid25_fpToFxPTest_b_4(DELAY,91) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist4_signX_uid25_fpToFxPTest_b_4 ( .xin(redist3_signX_uid25_fpToFxPTest_b_3_q), .xout(redist4_signX_uid25_fpToFxPTest_b_4_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // udfExpVal_uid29_fpToFxPTest(CONSTANT,28) + assign udfExpVal_uid29_fpToFxPTest_q = 8'b01111101; + + // udf_uid30_fpToFxPTest(COMPARE,29)@0 + 1 + assign udf_uid30_fpToFxPTest_a = {{3{udfExpVal_uid29_fpToFxPTest_q[7]}}, udfExpVal_uid29_fpToFxPTest_q}; + assign udf_uid30_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + udf_uid30_fpToFxPTest_o <= 11'b0; + end + else if (en == 1'b1) + begin + udf_uid30_fpToFxPTest_o <= $signed(udf_uid30_fpToFxPTest_a) - $signed(udf_uid30_fpToFxPTest_b); + end + end + assign udf_uid30_fpToFxPTest_n[0] = ~ (udf_uid30_fpToFxPTest_o[10]); + + // redist1_udf_uid30_fpToFxPTest_n_4(DELAY,88) + dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") ) + redist1_udf_uid30_fpToFxPTest_n_4 ( .xin(udf_uid30_fpToFxPTest_n), .xout(redist1_udf_uid30_fpToFxPTest_n_4_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // sPostRndFullMSBU_uid46_fpToFxPTest(BITSELECT,45)@3 + assign sPostRndFullMSBU_uid46_fpToFxPTest_in = sPostRndFull_uid44_fpToFxPTest_q[33:0]; + assign sPostRndFullMSBU_uid46_fpToFxPTest_b = sPostRndFullMSBU_uid46_fpToFxPTest_in[33:33]; + + // ovfExpVal_uid26_fpToFxPTest(CONSTANT,25) + assign ovfExpVal_uid26_fpToFxPTest_q = 9'b010011111; + + // ovf_uid27_fpToFxPTest(COMPARE,26)@0 + 1 + assign ovf_uid27_fpToFxPTest_a = {3'b000, exp_x_uid9_fpToFxPTest_b}; + assign ovf_uid27_fpToFxPTest_b = {{2{ovfExpVal_uid26_fpToFxPTest_q[8]}}, ovfExpVal_uid26_fpToFxPTest_q}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + ovf_uid27_fpToFxPTest_o <= 11'b0; + end + else if (en == 1'b1) + begin + ovf_uid27_fpToFxPTest_o <= $signed(ovf_uid27_fpToFxPTest_a) - $signed(ovf_uid27_fpToFxPTest_b); + end + end + assign ovf_uid27_fpToFxPTest_n[0] = ~ (ovf_uid27_fpToFxPTest_o[10]); + + // redist2_ovf_uid27_fpToFxPTest_n_3(DELAY,89) + dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") ) + redist2_ovf_uid27_fpToFxPTest_n_3 ( .xin(ovf_uid27_fpToFxPTest_n), .xout(redist2_ovf_uid27_fpToFxPTest_n_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // negOrOvf_uid28_fpToFxPTest(LOGICAL,27)@3 + assign negOrOvf_uid28_fpToFxPTest_q = redist3_signX_uid25_fpToFxPTest_b_3_q | redist2_ovf_uid27_fpToFxPTest_n_3_q; + + // cstZeroWF_uid7_fpToFxPTest(CONSTANT,6) + assign cstZeroWF_uid7_fpToFxPTest_q = 23'b00000000000000000000000; + + // fracXIsZero_uid13_fpToFxPTest(LOGICAL,12)@2 + 1 + assign fracXIsZero_uid13_fpToFxPTest_qi = cstZeroWF_uid7_fpToFxPTest_q == redist7_frac_x_uid10_fpToFxPTest_b_2_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + fracXIsZero_uid13_fpToFxPTest_delay ( .xin(fracXIsZero_uid13_fpToFxPTest_qi), .xout(fracXIsZero_uid13_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // cstAllOWE_uid6_fpToFxPTest(CONSTANT,5) + assign cstAllOWE_uid6_fpToFxPTest_q = 8'b11111111; + + // expXIsMax_uid12_fpToFxPTest(LOGICAL,11)@0 + 1 + assign expXIsMax_uid12_fpToFxPTest_qi = exp_x_uid9_fpToFxPTest_b == cstAllOWE_uid6_fpToFxPTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + expXIsMax_uid12_fpToFxPTest_delay ( .xin(expXIsMax_uid12_fpToFxPTest_qi), .xout(expXIsMax_uid12_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist5_expXIsMax_uid12_fpToFxPTest_q_3(DELAY,92) + dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") ) + redist5_expXIsMax_uid12_fpToFxPTest_q_3 ( .xin(expXIsMax_uid12_fpToFxPTest_q), .xout(redist5_expXIsMax_uid12_fpToFxPTest_q_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excI_x_uid15_fpToFxPTest(LOGICAL,14)@3 + assign excI_x_uid15_fpToFxPTest_q = redist5_expXIsMax_uid12_fpToFxPTest_q_3_q & fracXIsZero_uid13_fpToFxPTest_q; + + // fracXIsNotZero_uid14_fpToFxPTest(LOGICAL,13)@3 + assign fracXIsNotZero_uid14_fpToFxPTest_q = ~ (fracXIsZero_uid13_fpToFxPTest_q); + + // excN_x_uid16_fpToFxPTest(LOGICAL,15)@3 + assign excN_x_uid16_fpToFxPTest_q = redist5_expXIsMax_uid12_fpToFxPTest_q_3_q & fracXIsNotZero_uid14_fpToFxPTest_q; + + // ovfPostRnd_uid47_fpToFxPTest(LOGICAL,46)@3 + 1 + assign ovfPostRnd_uid47_fpToFxPTest_qi = excN_x_uid16_fpToFxPTest_q | excI_x_uid15_fpToFxPTest_q | negOrOvf_uid28_fpToFxPTest_q | sPostRndFullMSBU_uid46_fpToFxPTest_b; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + ovfPostRnd_uid47_fpToFxPTest_delay ( .xin(ovfPostRnd_uid47_fpToFxPTest_qi), .xout(ovfPostRnd_uid47_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // muxSelConc_uid48_fpToFxPTest(BITJOIN,47)@4 + assign muxSelConc_uid48_fpToFxPTest_q = {redist4_signX_uid25_fpToFxPTest_b_4_q, redist1_udf_uid30_fpToFxPTest_n_4_q, ovfPostRnd_uid47_fpToFxPTest_q}; + + // muxSel_uid49_fpToFxPTest(LOOKUP,48)@4 + always @(muxSelConc_uid48_fpToFxPTest_q) + begin + // Begin reserved scope level + unique case (muxSelConc_uid48_fpToFxPTest_q) + 3'b000 : muxSel_uid49_fpToFxPTest_q = 2'b00; + 3'b001 : muxSel_uid49_fpToFxPTest_q = 2'b01; + 3'b010 : muxSel_uid49_fpToFxPTest_q = 2'b11; + 3'b011 : muxSel_uid49_fpToFxPTest_q = 2'b00; + 3'b100 : muxSel_uid49_fpToFxPTest_q = 2'b10; + 3'b101 : muxSel_uid49_fpToFxPTest_q = 2'b10; + 3'b110 : muxSel_uid49_fpToFxPTest_q = 2'b10; + 3'b111 : muxSel_uid49_fpToFxPTest_q = 2'b10; + default : begin + // unreachable + muxSel_uid49_fpToFxPTest_q = 2'bxx; + end + endcase + // End reserved scope level + end + + // finalOut_uid51_fpToFxPTest(MUX,50)@4 + assign finalOut_uid51_fpToFxPTest_s = muxSel_uid49_fpToFxPTest_q; + always @(finalOut_uid51_fpToFxPTest_s or en or redist0_sPostRnd_uid45_fpToFxPTest_b_1_q or maxPosValueU_uid40_fpToFxPTest_q or maxNegValueU_uid41_fpToFxPTest_q) + begin + unique case (finalOut_uid51_fpToFxPTest_s) + 2'b00 : finalOut_uid51_fpToFxPTest_q = redist0_sPostRnd_uid45_fpToFxPTest_b_1_q; + 2'b01 : finalOut_uid51_fpToFxPTest_q = maxPosValueU_uid40_fpToFxPTest_q; + 2'b10 : finalOut_uid51_fpToFxPTest_q = maxNegValueU_uid41_fpToFxPTest_q; + 2'b11 : finalOut_uid51_fpToFxPTest_q = maxNegValueU_uid41_fpToFxPTest_q; + default : finalOut_uid51_fpToFxPTest_q = 32'b0; + endcase + end + + // xOut(GPOUT,4)@4 + assign q = finalOut_uid51_fpToFxPTest_q; + +endmodule diff --git a/hw/rtl/fp_cores/altera/acl_fp_itof.sv b/hw/rtl/fp_cores/altera/acl_fp_itof.sv new file mode 100644 index 00000000..43b15b93 --- /dev/null +++ b/hw/rtl/fp_cores/altera/acl_fp_itof.sv @@ -0,0 +1,522 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_fp_itof +// SystemVerilog created on Wed Aug 5 12:58:15 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_fp_itof ( + input wire [31:0] a, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire [0:0] GND_q; + wire [0:0] signX_uid6_fxpToFPTest_b; + wire [31:0] xXorSign_uid7_fxpToFPTest_b; + wire [31:0] xXorSign_uid7_fxpToFPTest_q; + wire [32:0] yE_uid8_fxpToFPTest_a; + wire [32:0] yE_uid8_fxpToFPTest_b; + logic [32:0] yE_uid8_fxpToFPTest_o; + wire [32:0] yE_uid8_fxpToFPTest_q; + wire [31:0] y_uid9_fxpToFPTest_in; + wire [31:0] y_uid9_fxpToFPTest_b; + wire [5:0] maxCount_uid11_fxpToFPTest_q; + wire [0:0] inIsZero_uid12_fxpToFPTest_qi; + reg [0:0] inIsZero_uid12_fxpToFPTest_q; + wire [7:0] msbIn_uid13_fxpToFPTest_q; + wire [8:0] expPreRnd_uid14_fxpToFPTest_a; + wire [8:0] expPreRnd_uid14_fxpToFPTest_b; + logic [8:0] expPreRnd_uid14_fxpToFPTest_o; + wire [8:0] expPreRnd_uid14_fxpToFPTest_q; + wire [32:0] expFracRnd_uid16_fxpToFPTest_q; + wire [0:0] sticky_uid20_fxpToFPTest_qi; + reg [0:0] sticky_uid20_fxpToFPTest_q; + wire [0:0] nr_uid21_fxpToFPTest_q; + wire [0:0] rnd_uid22_fxpToFPTest_qi; + reg [0:0] rnd_uid22_fxpToFPTest_q; + wire [34:0] expFracR_uid24_fxpToFPTest_a; + wire [34:0] expFracR_uid24_fxpToFPTest_b; + logic [34:0] expFracR_uid24_fxpToFPTest_o; + wire [33:0] expFracR_uid24_fxpToFPTest_q; + wire [23:0] fracR_uid25_fxpToFPTest_in; + wire [22:0] fracR_uid25_fxpToFPTest_b; + wire [9:0] expR_uid26_fxpToFPTest_b; + wire [11:0] udf_uid27_fxpToFPTest_a; + wire [11:0] udf_uid27_fxpToFPTest_b; + logic [11:0] udf_uid27_fxpToFPTest_o; + wire [0:0] udf_uid27_fxpToFPTest_n; + wire [7:0] expInf_uid28_fxpToFPTest_q; + wire [11:0] ovf_uid29_fxpToFPTest_a; + wire [11:0] ovf_uid29_fxpToFPTest_b; + logic [11:0] ovf_uid29_fxpToFPTest_o; + wire [0:0] ovf_uid29_fxpToFPTest_n; + wire [0:0] excSelector_uid30_fxpToFPTest_q; + wire [22:0] fracZ_uid31_fxpToFPTest_q; + wire [0:0] fracRPostExc_uid32_fxpToFPTest_s; + reg [22:0] fracRPostExc_uid32_fxpToFPTest_q; + wire [0:0] udfOrInZero_uid33_fxpToFPTest_q; + wire [1:0] excSelector_uid34_fxpToFPTest_q; + wire [7:0] expZ_uid37_fxpToFPTest_q; + wire [7:0] expR_uid38_fxpToFPTest_in; + wire [7:0] expR_uid38_fxpToFPTest_b; + wire [1:0] expRPostExc_uid39_fxpToFPTest_s; + reg [7:0] expRPostExc_uid39_fxpToFPTest_q; + wire [31:0] outRes_uid40_fxpToFPTest_q; + wire [31:0] zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi; + reg [0:0] vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s; + reg [31:0] vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [15:0] zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [31:0] cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s; + reg [31:0] vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [31:0] cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s; + reg [31:0] vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [3:0] zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [31:0] cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s; + reg [31:0] vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [1:0] zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [31:0] cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s; + reg [31:0] vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [31:0] cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [0:0] vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s; + reg [31:0] vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [5:0] vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a; + wire [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b; + logic [7:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o; + wire [0:0] vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c; + wire [0:0] vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s; + reg [5:0] vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q; + wire [1:0] l_uid17_fxpToFPTest_merged_bit_select_in; + wire [0:0] l_uid17_fxpToFPTest_merged_bit_select_b; + wire [0:0] l_uid17_fxpToFPTest_merged_bit_select_c; + wire [15:0] rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b; + wire [15:0] rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c; + wire [7:0] rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b; + wire [23:0] rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c; + wire [3:0] rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b; + wire [27:0] rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c; + wire [1:0] rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b; + wire [29:0] rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c; + wire [0:0] rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b; + wire [30:0] rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c; + wire [30:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_in; + wire [23:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_b; + wire [6:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_c; + reg [23:0] redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1_q; + reg [0:0] redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1_q; + reg [0:0] redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q; + reg [0:0] redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_q; + reg [0:0] redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_q; + reg [0:0] redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_q; + reg [9:0] redist6_expR_uid26_fxpToFPTest_b_1_q; + reg [22:0] redist7_fracR_uid25_fxpToFPTest_b_1_q; + reg [32:0] redist8_expFracRnd_uid16_fxpToFPTest_q_1_q; + reg [0:0] redist9_inIsZero_uid12_fxpToFPTest_q_2_q; + reg [31:0] redist10_y_uid9_fxpToFPTest_b_1_q; + reg [31:0] redist11_y_uid9_fxpToFPTest_b_2_q; + reg [0:0] redist12_signX_uid6_fxpToFPTest_b_8_q; + + + // signX_uid6_fxpToFPTest(BITSELECT,5)@0 + assign signX_uid6_fxpToFPTest_b = a[31:31]; + + // redist12_signX_uid6_fxpToFPTest_b_8(DELAY,107) + dspba_delay_ver #( .width(1), .depth(8), .reset_kind("ASYNC") ) + redist12_signX_uid6_fxpToFPTest_b_8 ( .xin(signX_uid6_fxpToFPTest_b), .xout(redist12_signX_uid6_fxpToFPTest_b_8_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expInf_uid28_fxpToFPTest(CONSTANT,27) + assign expInf_uid28_fxpToFPTest_q = 8'b11111111; + + // expZ_uid37_fxpToFPTest(CONSTANT,36) + assign expZ_uid37_fxpToFPTest_q = 8'b00000000; + + // rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,93)@5 + assign rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q[31:31]; + assign rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q[30:0]; + + // GND(CONSTANT,0) + assign GND_q = 1'b0; + + // cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,79)@5 + assign cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, GND_q}; + + // rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,92)@4 + assign rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q[31:30]; + assign rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q[29:0]; + + // zs_uid68_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,67) + assign zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q = 2'b00; + + // cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,72)@4 + assign cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q}; + + // rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,91)@4 + assign rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q[31:28]; + assign rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q[27:0]; + + // zs_uid61_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,60) + assign zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q = 4'b0000; + + // cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,65)@4 + assign cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q}; + + // rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,90)@3 + assign rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q[31:24]; + assign rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q[23:0]; + + // cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,58)@3 + assign cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, expZ_uid37_fxpToFPTest_q}; + + // rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,89)@2 + assign rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q[31:16]; + assign rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q[15:0]; + + // zs_uid47_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,46) + assign zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q = 16'b0000000000000000; + + // cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,51)@2 + assign cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q}; + + // zs_uid42_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,41) + assign zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b00000000000000000000000000000000; + + // xXorSign_uid7_fxpToFPTest(LOGICAL,6)@0 + assign xXorSign_uid7_fxpToFPTest_b = {{31{signX_uid6_fxpToFPTest_b[0]}}, signX_uid6_fxpToFPTest_b}; + assign xXorSign_uid7_fxpToFPTest_q = a ^ xXorSign_uid7_fxpToFPTest_b; + + // yE_uid8_fxpToFPTest(ADD,7)@0 + assign yE_uid8_fxpToFPTest_a = {1'b0, xXorSign_uid7_fxpToFPTest_q}; + assign yE_uid8_fxpToFPTest_b = {32'b00000000000000000000000000000000, signX_uid6_fxpToFPTest_b}; + assign yE_uid8_fxpToFPTest_o = $unsigned(yE_uid8_fxpToFPTest_a) + $unsigned(yE_uid8_fxpToFPTest_b); + assign yE_uid8_fxpToFPTest_q = yE_uid8_fxpToFPTest_o[32:0]; + + // y_uid9_fxpToFPTest(BITSELECT,8)@0 + assign y_uid9_fxpToFPTest_in = yE_uid8_fxpToFPTest_q[31:0]; + assign y_uid9_fxpToFPTest_b = y_uid9_fxpToFPTest_in[31:0]; + + // redist10_y_uid9_fxpToFPTest_b_1(DELAY,105) + dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") ) + redist10_y_uid9_fxpToFPTest_b_1 ( .xin(y_uid9_fxpToFPTest_b), .xout(redist10_y_uid9_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist11_y_uid9_fxpToFPTest_b_2(DELAY,106) + dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") ) + redist11_y_uid9_fxpToFPTest_b_2 ( .xin(redist10_y_uid9_fxpToFPTest_b_1_q), .xout(redist11_y_uid9_fxpToFPTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,43)@1 + 1 + assign vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi = redist10_y_uid9_fxpToFPTest_b_1_q == zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_delay ( .xin(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi), .xout(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest(MUX,45)@2 + assign vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q; + always @(vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s or en or redist11_y_uid9_fxpToFPTest_b_2_q or zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q) + begin + unique case (vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s) + 1'b0 : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = redist11_y_uid9_fxpToFPTest_b_2_q; + 1'b1 : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q; + default : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0; + endcase + end + + // vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,48)@2 + assign vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid48_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid47_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0; + + // vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest(MUX,52)@2 + 1 + assign vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0; + end + else if (en == 1'b1) + begin + unique case (vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_s) + 1'b0 : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q; + 1'b1 : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= cStage_uid52_lzcShifterZ1_uid10_fxpToFPTest_q; + default : vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0; + endcase + end + end + + // vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,55)@3 + assign vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == expZ_uid37_fxpToFPTest_q ? 1'b1 : 1'b0; + + // vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest(MUX,59)@3 + 1 + assign vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0; + end + else if (en == 1'b1) + begin + unique case (vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s) + 1'b0 : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q <= vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q; + 1'b1 : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q <= cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q; + default : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0; + endcase + end + end + + // vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,62)@4 + assign vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0; + + // vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest(MUX,66)@4 + assign vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q; + always @(vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s or en or vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q or cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q) + begin + unique case (vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s) + 1'b0 : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q = vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q; + 1'b1 : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q = cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q; + default : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0; + endcase + end + + // vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,69)@4 + assign vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0; + + // vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest(MUX,73)@4 + 1 + assign vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0; + end + else if (en == 1'b1) + begin + unique case (vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s) + 1'b0 : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q <= vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q; + 1'b1 : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q <= cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q; + default : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0; + endcase + end + end + + // vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,76)@5 + assign vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == GND_q ? 1'b1 : 1'b0; + + // vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest(MUX,80)@5 + assign vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q; + always @(vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s or en or vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q or cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q) + begin + unique case (vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s) + 1'b0 : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q; + 1'b1 : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q; + default : vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0; + endcase + end + + // fracRnd_uid15_fxpToFPTest_merged_bit_select(BITSELECT,94)@5 + assign fracRnd_uid15_fxpToFPTest_merged_bit_select_in = vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q[30:0]; + assign fracRnd_uid15_fxpToFPTest_merged_bit_select_b = fracRnd_uid15_fxpToFPTest_merged_bit_select_in[30:7]; + assign fracRnd_uid15_fxpToFPTest_merged_bit_select_c = fracRnd_uid15_fxpToFPTest_merged_bit_select_in[6:0]; + + // sticky_uid20_fxpToFPTest(LOGICAL,19)@5 + 1 + assign sticky_uid20_fxpToFPTest_qi = fracRnd_uid15_fxpToFPTest_merged_bit_select_c != 7'b0000000 ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + sticky_uid20_fxpToFPTest_delay ( .xin(sticky_uid20_fxpToFPTest_qi), .xout(sticky_uid20_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // nr_uid21_fxpToFPTest(LOGICAL,20)@6 + assign nr_uid21_fxpToFPTest_q = ~ (l_uid17_fxpToFPTest_merged_bit_select_c); + + // maxCount_uid11_fxpToFPTest(CONSTANT,10) + assign maxCount_uid11_fxpToFPTest_q = 6'b100000; + + // redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4(DELAY,100) + dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") ) + redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4 ( .xin(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3(DELAY,99) + dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") ) + redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3 ( .xin(vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2(DELAY,98) + dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") ) + redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2 ( .xin(vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1(DELAY,97) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1 ( .xin(vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1(DELAY,96) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1 ( .xin(vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,81)@5 + assign vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q = {redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_q, redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_q, redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_q, redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q, redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1_q, vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q}; + + // vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest(COMPARE,83)@5 + assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a = {2'b00, maxCount_uid11_fxpToFPTest_q}; + assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b = {2'b00, vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q}; + assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o = $unsigned(vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a) - $unsigned(vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b); + assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c[0] = vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o[7]; + + // vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest(MUX,85)@5 + 1 + assign vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s = vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q <= 6'b0; + end + else if (en == 1'b1) + begin + unique case (vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s) + 1'b0 : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q <= vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q; + 1'b1 : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q <= maxCount_uid11_fxpToFPTest_q; + default : vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q <= 6'b0; + endcase + end + end + + // msbIn_uid13_fxpToFPTest(CONSTANT,12) + assign msbIn_uid13_fxpToFPTest_q = 8'b10011110; + + // expPreRnd_uid14_fxpToFPTest(SUB,13)@6 + assign expPreRnd_uid14_fxpToFPTest_a = {1'b0, msbIn_uid13_fxpToFPTest_q}; + assign expPreRnd_uid14_fxpToFPTest_b = {3'b000, vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q}; + assign expPreRnd_uid14_fxpToFPTest_o = $unsigned(expPreRnd_uid14_fxpToFPTest_a) - $unsigned(expPreRnd_uid14_fxpToFPTest_b); + assign expPreRnd_uid14_fxpToFPTest_q = expPreRnd_uid14_fxpToFPTest_o[8:0]; + + // redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1(DELAY,95) + dspba_delay_ver #( .width(24), .depth(1), .reset_kind("ASYNC") ) + redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1 ( .xin(fracRnd_uid15_fxpToFPTest_merged_bit_select_b), .xout(redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expFracRnd_uid16_fxpToFPTest(BITJOIN,15)@6 + assign expFracRnd_uid16_fxpToFPTest_q = {expPreRnd_uid14_fxpToFPTest_q, redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1_q}; + + // l_uid17_fxpToFPTest_merged_bit_select(BITSELECT,88)@6 + assign l_uid17_fxpToFPTest_merged_bit_select_in = expFracRnd_uid16_fxpToFPTest_q[1:0]; + assign l_uid17_fxpToFPTest_merged_bit_select_b = l_uid17_fxpToFPTest_merged_bit_select_in[1:1]; + assign l_uid17_fxpToFPTest_merged_bit_select_c = l_uid17_fxpToFPTest_merged_bit_select_in[0:0]; + + // rnd_uid22_fxpToFPTest(LOGICAL,21)@6 + 1 + assign rnd_uid22_fxpToFPTest_qi = l_uid17_fxpToFPTest_merged_bit_select_b | nr_uid21_fxpToFPTest_q | sticky_uid20_fxpToFPTest_q; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + rnd_uid22_fxpToFPTest_delay ( .xin(rnd_uid22_fxpToFPTest_qi), .xout(rnd_uid22_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist8_expFracRnd_uid16_fxpToFPTest_q_1(DELAY,103) + dspba_delay_ver #( .width(33), .depth(1), .reset_kind("ASYNC") ) + redist8_expFracRnd_uid16_fxpToFPTest_q_1 ( .xin(expFracRnd_uid16_fxpToFPTest_q), .xout(redist8_expFracRnd_uid16_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expFracR_uid24_fxpToFPTest(ADD,23)@7 + assign expFracR_uid24_fxpToFPTest_a = {{2{redist8_expFracRnd_uid16_fxpToFPTest_q_1_q[32]}}, redist8_expFracRnd_uid16_fxpToFPTest_q_1_q}; + assign expFracR_uid24_fxpToFPTest_b = {34'b0000000000000000000000000000000000, rnd_uid22_fxpToFPTest_q}; + assign expFracR_uid24_fxpToFPTest_o = $signed(expFracR_uid24_fxpToFPTest_a) + $signed(expFracR_uid24_fxpToFPTest_b); + assign expFracR_uid24_fxpToFPTest_q = expFracR_uid24_fxpToFPTest_o[33:0]; + + // expR_uid26_fxpToFPTest(BITSELECT,25)@7 + assign expR_uid26_fxpToFPTest_b = expFracR_uid24_fxpToFPTest_q[33:24]; + + // redist6_expR_uid26_fxpToFPTest_b_1(DELAY,101) + dspba_delay_ver #( .width(10), .depth(1), .reset_kind("ASYNC") ) + redist6_expR_uid26_fxpToFPTest_b_1 ( .xin(expR_uid26_fxpToFPTest_b), .xout(redist6_expR_uid26_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expR_uid38_fxpToFPTest(BITSELECT,37)@8 + assign expR_uid38_fxpToFPTest_in = redist6_expR_uid26_fxpToFPTest_b_1_q[7:0]; + assign expR_uid38_fxpToFPTest_b = expR_uid38_fxpToFPTest_in[7:0]; + + // ovf_uid29_fxpToFPTest(COMPARE,28)@8 + assign ovf_uid29_fxpToFPTest_a = {{2{redist6_expR_uid26_fxpToFPTest_b_1_q[9]}}, redist6_expR_uid26_fxpToFPTest_b_1_q}; + assign ovf_uid29_fxpToFPTest_b = {4'b0000, expInf_uid28_fxpToFPTest_q}; + assign ovf_uid29_fxpToFPTest_o = $signed(ovf_uid29_fxpToFPTest_a) - $signed(ovf_uid29_fxpToFPTest_b); + assign ovf_uid29_fxpToFPTest_n[0] = ~ (ovf_uid29_fxpToFPTest_o[11]); + + // inIsZero_uid12_fxpToFPTest(LOGICAL,11)@6 + 1 + assign inIsZero_uid12_fxpToFPTest_qi = vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q == maxCount_uid11_fxpToFPTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + inIsZero_uid12_fxpToFPTest_delay ( .xin(inIsZero_uid12_fxpToFPTest_qi), .xout(inIsZero_uid12_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist9_inIsZero_uid12_fxpToFPTest_q_2(DELAY,104) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist9_inIsZero_uid12_fxpToFPTest_q_2 ( .xin(inIsZero_uid12_fxpToFPTest_q), .xout(redist9_inIsZero_uid12_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // udf_uid27_fxpToFPTest(COMPARE,26)@8 + assign udf_uid27_fxpToFPTest_a = {11'b00000000000, GND_q}; + assign udf_uid27_fxpToFPTest_b = {{2{redist6_expR_uid26_fxpToFPTest_b_1_q[9]}}, redist6_expR_uid26_fxpToFPTest_b_1_q}; + assign udf_uid27_fxpToFPTest_o = $signed(udf_uid27_fxpToFPTest_a) - $signed(udf_uid27_fxpToFPTest_b); + assign udf_uid27_fxpToFPTest_n[0] = ~ (udf_uid27_fxpToFPTest_o[11]); + + // udfOrInZero_uid33_fxpToFPTest(LOGICAL,32)@8 + assign udfOrInZero_uid33_fxpToFPTest_q = udf_uid27_fxpToFPTest_n | redist9_inIsZero_uid12_fxpToFPTest_q_2_q; + + // excSelector_uid34_fxpToFPTest(BITJOIN,33)@8 + assign excSelector_uid34_fxpToFPTest_q = {ovf_uid29_fxpToFPTest_n, udfOrInZero_uid33_fxpToFPTest_q}; + + // expRPostExc_uid39_fxpToFPTest(MUX,38)@8 + assign expRPostExc_uid39_fxpToFPTest_s = excSelector_uid34_fxpToFPTest_q; + always @(expRPostExc_uid39_fxpToFPTest_s or en or expR_uid38_fxpToFPTest_b or expZ_uid37_fxpToFPTest_q or expInf_uid28_fxpToFPTest_q) + begin + unique case (expRPostExc_uid39_fxpToFPTest_s) + 2'b00 : expRPostExc_uid39_fxpToFPTest_q = expR_uid38_fxpToFPTest_b; + 2'b01 : expRPostExc_uid39_fxpToFPTest_q = expZ_uid37_fxpToFPTest_q; + 2'b10 : expRPostExc_uid39_fxpToFPTest_q = expInf_uid28_fxpToFPTest_q; + 2'b11 : expRPostExc_uid39_fxpToFPTest_q = expInf_uid28_fxpToFPTest_q; + default : expRPostExc_uid39_fxpToFPTest_q = 8'b0; + endcase + end + + // fracZ_uid31_fxpToFPTest(CONSTANT,30) + assign fracZ_uid31_fxpToFPTest_q = 23'b00000000000000000000000; + + // fracR_uid25_fxpToFPTest(BITSELECT,24)@7 + assign fracR_uid25_fxpToFPTest_in = expFracR_uid24_fxpToFPTest_q[23:0]; + assign fracR_uid25_fxpToFPTest_b = fracR_uid25_fxpToFPTest_in[23:1]; + + // redist7_fracR_uid25_fxpToFPTest_b_1(DELAY,102) + dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) + redist7_fracR_uid25_fxpToFPTest_b_1 ( .xin(fracR_uid25_fxpToFPTest_b), .xout(redist7_fracR_uid25_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excSelector_uid30_fxpToFPTest(LOGICAL,29)@8 + assign excSelector_uid30_fxpToFPTest_q = redist9_inIsZero_uid12_fxpToFPTest_q_2_q | ovf_uid29_fxpToFPTest_n | udf_uid27_fxpToFPTest_n; + + // fracRPostExc_uid32_fxpToFPTest(MUX,31)@8 + assign fracRPostExc_uid32_fxpToFPTest_s = excSelector_uid30_fxpToFPTest_q; + always @(fracRPostExc_uid32_fxpToFPTest_s or en or redist7_fracR_uid25_fxpToFPTest_b_1_q or fracZ_uid31_fxpToFPTest_q) + begin + unique case (fracRPostExc_uid32_fxpToFPTest_s) + 1'b0 : fracRPostExc_uid32_fxpToFPTest_q = redist7_fracR_uid25_fxpToFPTest_b_1_q; + 1'b1 : fracRPostExc_uid32_fxpToFPTest_q = fracZ_uid31_fxpToFPTest_q; + default : fracRPostExc_uid32_fxpToFPTest_q = 23'b0; + endcase + end + + // outRes_uid40_fxpToFPTest(BITJOIN,39)@8 + assign outRes_uid40_fxpToFPTest_q = {redist12_signX_uid6_fxpToFPTest_b_8_q, expRPostExc_uid39_fxpToFPTest_q, fracRPostExc_uid32_fxpToFPTest_q}; + + // xOut(GPOUT,4)@8 + assign q = outRes_uid40_fxpToFPTest_q; + +endmodule diff --git a/hw/rtl/fp_cores/altera/acl_fp_msub.v b/hw/rtl/fp_cores/altera/acl_fp_msub.v deleted file mode 100644 index 09c0de6a..00000000 --- a/hw/rtl/fp_cores/altera/acl_fp_msub.v +++ /dev/null @@ -1,63 +0,0 @@ -// (C) 1992-2014 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - -module acl_fp_multadd(dataa, datab, datac, clock, enable, result); -// a*b + c -input [31:0] dataa; -input [31:0] datab; -input [31:0] datac; -input clock; -input enable; -output [31:0] result; - -// FP MAC wysiwyg -twentynm_fp_mac mac_fp_wys ( - // inputs - .accumulate(), - .chainin_overflow(), - .chainin_invalid(), - .chainin_underflow(), - .chainin_inexact(), - .ax(datac), - .ay(datab), - .az(dataa), - .clk({2'b00,clock}), - .ena({2'b11,enable}), - .aclr(2'b00), - .chainin(), - // outputs - .overflow(), - .invalid(), - .underflow(), - .inexact(), - .chainout_overflow(), - .chainout_invalid(), - .chainout_underflow(), - .chainout_inexact(), - .resulta(result), - .chainout() -); -defparam mac_fp_wys.operation_mode = "sp_mult_add"; -defparam mac_fp_wys.use_chainin = "false"; -defparam mac_fp_wys.adder_subtract = "true"; -defparam mac_fp_wys.ax_clock = "0"; -defparam mac_fp_wys.ay_clock = "0"; -defparam mac_fp_wys.az_clock = "0"; -defparam mac_fp_wys.output_clock = "0"; -defparam mac_fp_wys.accumulate_clock = "none"; -defparam mac_fp_wys.ax_chainin_pl_clock = "0"; -defparam mac_fp_wys.accum_pipeline_clock = "none"; -defparam mac_fp_wys.mult_pipeline_clock = "0"; -defparam mac_fp_wys.adder_input_clock = "0"; -defparam mac_fp_wys.accum_adder_clock = "none"; - -endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/altera/acl_fp_mul.v b/hw/rtl/fp_cores/altera/acl_fp_mul.v deleted file mode 100644 index a19eda1d..00000000 --- a/hw/rtl/fp_cores/altera/acl_fp_mul.v +++ /dev/null @@ -1,67 +0,0 @@ -// (C) 1992-2016 Intel Corporation. -// Intel, the Intel logo, Intel, MegaCore, NIOS II, Quartus and TalkBack words -// and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. -// and/or other countries. Other marks and brands may be claimed as the property -// of others. See Trademarks on intel.com for full list of Intel trademarks or -// the Trademarks & Brands Names Database (if Intel) or See www.Intel.com/legal (if Altera) -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Intel MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - -module acl_fp_mul(dataa, datab, clock, enable, result); - -input [31:0] dataa; -input [31:0] datab; -input clock, enable; - -output [31:0] result; - -// FP MAC wysiwyg -twentynm_fp_mac mac_fp_wys ( - // inputs - .accumulate(), - .chainin_overflow(), - .chainin_invalid(), - .chainin_underflow(), - .chainin_inexact(), - .ax(), - .ay(datab), - .az(dataa), - .clk({2'b00,clock}), - .ena({2'b11,enable}), - .aclr(2'b00), - .chainin(), - // outputs - .overflow(), - .invalid(), - .underflow(), - .inexact(), - .chainout_overflow(), - .chainout_invalid(), - .chainout_underflow(), - .chainout_inexact(), - .resulta(result), - .chainout() -); -defparam mac_fp_wys.operation_mode = "sp_mult"; -defparam mac_fp_wys.use_chainin = "false"; -defparam mac_fp_wys.adder_subtract = "false"; -defparam mac_fp_wys.ax_clock = "none"; -defparam mac_fp_wys.ay_clock = "0"; -defparam mac_fp_wys.az_clock = "0"; -defparam mac_fp_wys.output_clock = "0"; -defparam mac_fp_wys.accumulate_clock = "none"; -defparam mac_fp_wys.ax_chainin_pl_clock = "none"; -defparam mac_fp_wys.accum_pipeline_clock = "none"; -defparam mac_fp_wys.mult_pipeline_clock = "0"; -defparam mac_fp_wys.adder_input_clock = "none"; -defparam mac_fp_wys.accum_adder_clock = "none"; - -endmodule diff --git a/hw/rtl/fp_cores/altera/acl_fp_nmadd.v b/hw/rtl/fp_cores/altera/acl_fp_nmadd.v deleted file mode 100644 index f7ad8aa8..00000000 --- a/hw/rtl/fp_cores/altera/acl_fp_nmadd.v +++ /dev/null @@ -1,63 +0,0 @@ -// (C) 1992-2014 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - -module acl_fp_multadd(dataa, datab, datac, clock, enable, result); -// a*b + c -input [31:0] dataa; -input [31:0] datab; -input [31:0] datac; -input clock; -input enable; -output [31:0] result; - -// FP MAC wysiwyg -twentynm_fp_mac mac_fp_wys ( - // inputs - .accumulate(), - .chainin_overflow(), - .chainin_invalid(), - .chainin_underflow(), - .chainin_inexact(), - .ax(datac), - .ay(datab), - .az(dataa), - .clk({2'b00,clock}), - .ena({2'b11,enable}), - .aclr(2'b00), - .chainin(), - // outputs - .overflow(), - .invalid(), - .underflow(), - .inexact(), - .chainout_overflow(), - .chainout_invalid(), - .chainout_underflow(), - .chainout_inexact(), - .resulta(result), - .chainout() -); -defparam mac_fp_wys.operation_mode = "sp_mult_add"; -defparam mac_fp_wys.use_chainin = "false"; -defparam mac_fp_wys.adder_subtract = "false"; -defparam mac_fp_wys.ax_clock = "0"; -defparam mac_fp_wys.ay_clock = "0"; -defparam mac_fp_wys.az_clock = "0"; -defparam mac_fp_wys.output_clock = "0"; -defparam mac_fp_wys.accumulate_clock = "none"; -defparam mac_fp_wys.ax_chainin_pl_clock = "0"; -defparam mac_fp_wys.accum_pipeline_clock = "none"; -defparam mac_fp_wys.mult_pipeline_clock = "0"; -defparam mac_fp_wys.adder_input_clock = "0"; -defparam mac_fp_wys.accum_adder_clock = "none"; - -endmodule \ No newline at end of file diff --git a/hw/rtl/fp_cores/altera/acl_fp_sqrt.sv b/hw/rtl/fp_cores/altera/acl_fp_sqrt.sv new file mode 100644 index 00000000..82888773 --- /dev/null +++ b/hw/rtl/fp_cores/altera/acl_fp_sqrt.sv @@ -0,0 +1,1128 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_fp_sqrt +// SystemVerilog created on Wed Aug 5 12:58:14 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_fp_sqrt ( + input wire [31:0] a, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire [0:0] GND_q; + wire [0:0] VCC_q; + wire [7:0] expX_uid6_fpSqrtTest_b; + wire [0:0] signX_uid7_fpSqrtTest_b; + wire [7:0] cstAllOWE_uid8_fpSqrtTest_q; + wire [22:0] cstZeroWF_uid9_fpSqrtTest_q; + wire [7:0] cstAllZWE_uid10_fpSqrtTest_q; + wire [22:0] frac_x_uid12_fpSqrtTest_b; + wire [0:0] excZ_x_uid13_fpSqrtTest_qi; + reg [0:0] excZ_x_uid13_fpSqrtTest_q; + wire [0:0] expXIsMax_uid14_fpSqrtTest_qi; + reg [0:0] expXIsMax_uid14_fpSqrtTest_q; + wire [0:0] fracXIsZero_uid15_fpSqrtTest_qi; + reg [0:0] fracXIsZero_uid15_fpSqrtTest_q; + wire [0:0] fracXIsNotZero_uid16_fpSqrtTest_q; + wire [0:0] excI_x_uid17_fpSqrtTest_q; + wire [0:0] excN_x_uid18_fpSqrtTest_q; + wire [0:0] invExpXIsMax_uid19_fpSqrtTest_q; + wire [0:0] InvExpXIsZero_uid20_fpSqrtTest_q; + wire [0:0] excR_x_uid21_fpSqrtTest_q; + wire [7:0] sBias_uid22_fpSqrtTest_q; + wire [8:0] expEvenSig_uid24_fpSqrtTest_a; + wire [8:0] expEvenSig_uid24_fpSqrtTest_b; + logic [8:0] expEvenSig_uid24_fpSqrtTest_o; + wire [8:0] expEvenSig_uid24_fpSqrtTest_q; + wire [7:0] expREven_uid25_fpSqrtTest_b; + wire [7:0] sBiasM1_uid26_fpSqrtTest_q; + wire [8:0] expOddSig_uid27_fpSqrtTest_a; + wire [8:0] expOddSig_uid27_fpSqrtTest_b; + logic [8:0] expOddSig_uid27_fpSqrtTest_o; + wire [8:0] expOddSig_uid27_fpSqrtTest_q; + wire [7:0] expROdd_uid28_fpSqrtTest_b; + wire [0:0] expX0PS_uid29_fpSqrtTest_in; + wire [0:0] expX0PS_uid29_fpSqrtTest_b; + wire [0:0] expOddSelect_uid30_fpSqrtTest_q; + wire [0:0] expRMux_uid31_fpSqrtTest_s; + reg [7:0] expRMux_uid31_fpSqrtTest_q; + wire [23:0] addrFull_uid33_fpSqrtTest_q; + wire [7:0] yAddr_uid35_fpSqrtTest_b; + wire [15:0] yForPe_uid36_fpSqrtTest_in; + wire [15:0] yForPe_uid36_fpSqrtTest_b; + wire [30:0] expInc_uid38_fpSqrtTest_in; + wire [0:0] expInc_uid38_fpSqrtTest_b; + wire [28:0] fracRPostProcessings_uid39_fpSqrtTest_in; + wire [22:0] fracRPostProcessings_uid39_fpSqrtTest_b; + wire [8:0] expR_uid40_fpSqrtTest_a; + wire [8:0] expR_uid40_fpSqrtTest_b; + logic [8:0] expR_uid40_fpSqrtTest_o; + wire [8:0] expR_uid40_fpSqrtTest_q; + wire [0:0] invSignX_uid41_fpSqrtTest_q; + wire [0:0] inInfAndNotNeg_uid42_fpSqrtTest_q; + wire [0:0] minReg_uid43_fpSqrtTest_q; + wire [0:0] minInf_uid44_fpSqrtTest_q; + wire [0:0] excRNaN_uid45_fpSqrtTest_q; + wire [2:0] excConc_uid46_fpSqrtTest_q; + wire [3:0] fracSelIn_uid47_fpSqrtTest_q; + reg [1:0] fracSel_uid48_fpSqrtTest_q; + wire [7:0] expRR_uid51_fpSqrtTest_in; + wire [7:0] expRR_uid51_fpSqrtTest_b; + wire [1:0] expRPostExc_uid53_fpSqrtTest_s; + reg [7:0] expRPostExc_uid53_fpSqrtTest_q; + wire [22:0] fracNaN_uid54_fpSqrtTest_q; + wire [1:0] fracRPostExc_uid58_fpSqrtTest_s; + reg [22:0] fracRPostExc_uid58_fpSqrtTest_q; + wire [0:0] negZero_uid59_fpSqrtTest_qi; + reg [0:0] negZero_uid59_fpSqrtTest_q; + wire [31:0] RSqrt_uid60_fpSqrtTest_q; + wire [11:0] yT1_uid74_invPolyEval_b; + wire [0:0] lowRangeB_uid76_invPolyEval_in; + wire [0:0] lowRangeB_uid76_invPolyEval_b; + wire [11:0] highBBits_uid77_invPolyEval_b; + wire [21:0] s1sumAHighB_uid78_invPolyEval_a; + wire [21:0] s1sumAHighB_uid78_invPolyEval_b; + logic [21:0] s1sumAHighB_uid78_invPolyEval_o; + wire [21:0] s1sumAHighB_uid78_invPolyEval_q; + wire [22:0] s1_uid79_invPolyEval_q; + wire [1:0] lowRangeB_uid82_invPolyEval_in; + wire [1:0] lowRangeB_uid82_invPolyEval_b; + wire [21:0] highBBits_uid83_invPolyEval_b; + wire [29:0] s2sumAHighB_uid84_invPolyEval_a; + wire [29:0] s2sumAHighB_uid84_invPolyEval_b; + logic [29:0] s2sumAHighB_uid84_invPolyEval_o; + wire [29:0] s2sumAHighB_uid84_invPolyEval_q; + wire [31:0] s2_uid85_invPolyEval_q; + wire [12:0] osig_uid88_pT1_uid75_invPolyEval_b; + wire [23:0] osig_uid91_pT2_uid81_invPolyEval_b; + wire memoryC0_uid62_sqrtTables_lutmem_reset0; + wire [28:0] memoryC0_uid62_sqrtTables_lutmem_ia; + wire [7:0] memoryC0_uid62_sqrtTables_lutmem_aa; + wire [7:0] memoryC0_uid62_sqrtTables_lutmem_ab; + wire [28:0] memoryC0_uid62_sqrtTables_lutmem_ir; + wire [28:0] memoryC0_uid62_sqrtTables_lutmem_r; + wire memoryC1_uid65_sqrtTables_lutmem_reset0; + wire [20:0] memoryC1_uid65_sqrtTables_lutmem_ia; + wire [7:0] memoryC1_uid65_sqrtTables_lutmem_aa; + wire [7:0] memoryC1_uid65_sqrtTables_lutmem_ab; + wire [20:0] memoryC1_uid65_sqrtTables_lutmem_ir; + wire [20:0] memoryC1_uid65_sqrtTables_lutmem_r; + wire memoryC2_uid68_sqrtTables_lutmem_reset0; + wire [11:0] memoryC2_uid68_sqrtTables_lutmem_ia; + wire [7:0] memoryC2_uid68_sqrtTables_lutmem_aa; + wire [7:0] memoryC2_uid68_sqrtTables_lutmem_ab; + wire [11:0] memoryC2_uid68_sqrtTables_lutmem_ir; + wire [11:0] memoryC2_uid68_sqrtTables_lutmem_r; + wire prodXY_uid87_pT1_uid75_invPolyEval_cma_reset; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [11:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_a0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [11:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_a1 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [11:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_c0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [11:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_c1 [0:0]; + wire signed [12:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_l [0:0]; + wire signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_p [0:0]; + wire signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_u [0:0]; + wire signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_w [0:0]; + wire signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_x [0:0]; + wire signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_y [0:0]; + reg signed [24:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_s [0:0]; + wire [23:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_qq; + wire [23:0] prodXY_uid87_pT1_uid75_invPolyEval_cma_q; + wire prodXY_uid87_pT1_uid75_invPolyEval_cma_ena0; + wire prodXY_uid87_pT1_uid75_invPolyEval_cma_ena1; + wire prodXY_uid87_pT1_uid75_invPolyEval_cma_ena2; + wire prodXY_uid90_pT2_uid81_invPolyEval_cma_reset; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [15:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_a0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg [15:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_a1 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [22:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_c0 [0:0]; + (* preserve, altera_attribute = "-name allow_synch_ctrl_usage off" *) reg signed [22:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_c1 [0:0]; + wire signed [16:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_l [0:0]; + wire signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_p [0:0]; + wire signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_u [0:0]; + wire signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_w [0:0]; + wire signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_x [0:0]; + wire signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_y [0:0]; + reg signed [39:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_s [0:0]; + wire [38:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_qq; + wire [38:0] prodXY_uid90_pT2_uid81_invPolyEval_cma_q; + wire prodXY_uid90_pT2_uid81_invPolyEval_cma_ena0; + wire prodXY_uid90_pT2_uid81_invPolyEval_cma_ena1; + wire prodXY_uid90_pT2_uid81_invPolyEval_cma_ena2; + reg [0:0] redist0_lowRangeB_uid76_invPolyEval_b_1_q; + reg [0:0] redist1_negZero_uid59_fpSqrtTest_q_9_q; + reg [1:0] redist2_fracSel_uid48_fpSqrtTest_q_9_q; + reg [22:0] redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1_q; + reg [0:0] redist4_expInc_uid38_fpSqrtTest_b_1_q; + reg [15:0] redist5_yForPe_uid36_fpSqrtTest_b_2_q; + reg [7:0] redist7_yAddr_uid35_fpSqrtTest_b_3_q; + reg [7:0] redist8_yAddr_uid35_fpSqrtTest_b_7_q; + reg [0:0] redist10_signX_uid7_fpSqrtTest_b_1_q; + wire redist6_yForPe_uid36_fpSqrtTest_b_6_mem_reset0; + wire [15:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ia; + wire [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_aa; + wire [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ab; + wire [15:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_iq; + wire [15:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_q; + wire [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_q; + (* preserve *) reg [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i; + (* preserve *) reg redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_eq; + wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_s; + reg [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q; + reg [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q; + wire [1:0] redist6_yForPe_uid36_fpSqrtTest_b_6_mem_last_q; + wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_cmp_q; + reg [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_cmpReg_q; + wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_notEnable_q; + wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_nor_q; + (* preserve_syn_only *) reg [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena_q; + wire [0:0] redist6_yForPe_uid36_fpSqrtTest_b_6_enaAnd_q; + reg [7:0] redist9_expRMux_uid31_fpSqrtTest_q_10_outputreg_q; + wire redist9_expRMux_uid31_fpSqrtTest_q_10_mem_reset0; + wire [7:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ia; + wire [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_aa; + wire [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ab; + wire [7:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_iq; + wire [7:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_q; + wire [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_q; + (* preserve *) reg [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i; + (* preserve *) reg redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_eq; + wire [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_s; + reg [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q; + reg [2:0] redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q; + wire [3:0] redist9_expRMux_uid31_fpSqrtTest_q_10_mem_last_q; + wire [3:0] redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_b; + wire [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_q; + reg [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_cmpReg_q; + wire [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_notEnable_q; + wire [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_nor_q; + (* preserve_syn_only *) reg [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena_q; + wire [0:0] redist9_expRMux_uid31_fpSqrtTest_q_10_enaAnd_q; + + + // signX_uid7_fpSqrtTest(BITSELECT,6)@0 + assign signX_uid7_fpSqrtTest_b = a[31:31]; + + // redist10_signX_uid7_fpSqrtTest_b_1(DELAY,107) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist10_signX_uid7_fpSqrtTest_b_1 ( .xin(signX_uid7_fpSqrtTest_b), .xout(redist10_signX_uid7_fpSqrtTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // cstAllZWE_uid10_fpSqrtTest(CONSTANT,9) + assign cstAllZWE_uid10_fpSqrtTest_q = 8'b00000000; + + // expX_uid6_fpSqrtTest(BITSELECT,5)@0 + assign expX_uid6_fpSqrtTest_b = a[30:23]; + + // excZ_x_uid13_fpSqrtTest(LOGICAL,12)@0 + 1 + assign excZ_x_uid13_fpSqrtTest_qi = expX_uid6_fpSqrtTest_b == cstAllZWE_uid10_fpSqrtTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + excZ_x_uid13_fpSqrtTest_delay ( .xin(excZ_x_uid13_fpSqrtTest_qi), .xout(excZ_x_uid13_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // negZero_uid59_fpSqrtTest(LOGICAL,58)@1 + 1 + assign negZero_uid59_fpSqrtTest_qi = excZ_x_uid13_fpSqrtTest_q & redist10_signX_uid7_fpSqrtTest_b_1_q; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + negZero_uid59_fpSqrtTest_delay ( .xin(negZero_uid59_fpSqrtTest_qi), .xout(negZero_uid59_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist1_negZero_uid59_fpSqrtTest_q_9(DELAY,98) + dspba_delay_ver #( .width(1), .depth(8), .reset_kind("ASYNC") ) + redist1_negZero_uid59_fpSqrtTest_q_9 ( .xin(negZero_uid59_fpSqrtTest_q), .xout(redist1_negZero_uid59_fpSqrtTest_q_9_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // cstAllOWE_uid8_fpSqrtTest(CONSTANT,7) + assign cstAllOWE_uid8_fpSqrtTest_q = 8'b11111111; + + // expX0PS_uid29_fpSqrtTest(BITSELECT,28)@0 + assign expX0PS_uid29_fpSqrtTest_in = expX_uid6_fpSqrtTest_b[0:0]; + assign expX0PS_uid29_fpSqrtTest_b = expX0PS_uid29_fpSqrtTest_in[0:0]; + + // expOddSelect_uid30_fpSqrtTest(LOGICAL,29)@0 + assign expOddSelect_uid30_fpSqrtTest_q = ~ (expX0PS_uid29_fpSqrtTest_b); + + // frac_x_uid12_fpSqrtTest(BITSELECT,11)@0 + assign frac_x_uid12_fpSqrtTest_b = a[22:0]; + + // addrFull_uid33_fpSqrtTest(BITJOIN,32)@0 + assign addrFull_uid33_fpSqrtTest_q = {expOddSelect_uid30_fpSqrtTest_q, frac_x_uid12_fpSqrtTest_b}; + + // yAddr_uid35_fpSqrtTest(BITSELECT,34)@0 + assign yAddr_uid35_fpSqrtTest_b = addrFull_uid33_fpSqrtTest_q[23:16]; + + // memoryC2_uid68_sqrtTables_lutmem(DUALMEM,94)@0 + 2 + // in j@20000000 + assign memoryC2_uid68_sqrtTables_lutmem_aa = yAddr_uid35_fpSqrtTest_b; + assign memoryC2_uid68_sqrtTables_lutmem_reset0 = areset; + altera_syncram #( + .ram_block_type("M20K"), + .operation_mode("ROM"), + .width_a(12), + .widthad_a(8), + .numwords_a(256), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .outdata_reg_a("CLOCK0"), + .outdata_aclr_a("CLEAR0"), + .clock_enable_input_a("NORMAL"), + .power_up_uninitialized("FALSE"), + .init_file("acl_fp_sqrt_memoryC2_uid68_sqrtTables_lutmem.hex"), + .init_file_layout("PORT_A"), + .intended_device_family("Arria 10") + ) memoryC2_uid68_sqrtTables_lutmem_dmem ( + .clocken0(en[0]), + .aclr0(memoryC2_uid68_sqrtTables_lutmem_reset0), + .clock0(clk), + .address_a(memoryC2_uid68_sqrtTables_lutmem_aa), + .q_a(memoryC2_uid68_sqrtTables_lutmem_ir), + .wren_a(), + .wren_b(), + .rden_a(), + .rden_b(), + .data_a(), + .data_b(), + .address_b(), + .clock1(), + .clocken1(), + .clocken2(), + .clocken3(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_b(), + .eccstatus() + ); + assign memoryC2_uid68_sqrtTables_lutmem_r = memoryC2_uid68_sqrtTables_lutmem_ir[11:0]; + + // yForPe_uid36_fpSqrtTest(BITSELECT,35)@0 + assign yForPe_uid36_fpSqrtTest_in = frac_x_uid12_fpSqrtTest_b[15:0]; + assign yForPe_uid36_fpSqrtTest_b = yForPe_uid36_fpSqrtTest_in[15:0]; + + // redist5_yForPe_uid36_fpSqrtTest_b_2(DELAY,102) + dspba_delay_ver #( .width(16), .depth(2), .reset_kind("ASYNC") ) + redist5_yForPe_uid36_fpSqrtTest_b_2 ( .xin(yForPe_uid36_fpSqrtTest_b), .xout(redist5_yForPe_uid36_fpSqrtTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // yT1_uid74_invPolyEval(BITSELECT,73)@2 + assign yT1_uid74_invPolyEval_b = redist5_yForPe_uid36_fpSqrtTest_b_2_q[15:4]; + + // prodXY_uid87_pT1_uid75_invPolyEval_cma(CHAINMULTADD,95)@2 + 3 + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_reset = areset; + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_ena0 = en[0]; + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_ena1 = prodXY_uid87_pT1_uid75_invPolyEval_cma_ena0; + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_ena2 = prodXY_uid87_pT1_uid75_invPolyEval_cma_ena0; + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid87_pT1_uid75_invPolyEval_cma_a1[0][11:0]}); + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_p[0] = prodXY_uid87_pT1_uid75_invPolyEval_cma_l[0] * prodXY_uid87_pT1_uid75_invPolyEval_cma_c1[0]; + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_u[0] = prodXY_uid87_pT1_uid75_invPolyEval_cma_p[0][24:0]; + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_w[0] = prodXY_uid87_pT1_uid75_invPolyEval_cma_u[0]; + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_x[0] = prodXY_uid87_pT1_uid75_invPolyEval_cma_w[0]; + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_y[0] = prodXY_uid87_pT1_uid75_invPolyEval_cma_x[0]; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid87_pT1_uid75_invPolyEval_cma_a0 <= '{default: '0}; + prodXY_uid87_pT1_uid75_invPolyEval_cma_c0 <= '{default: '0}; + end + else + begin + if (prodXY_uid87_pT1_uid75_invPolyEval_cma_ena0 == 1'b1) + begin + prodXY_uid87_pT1_uid75_invPolyEval_cma_a0[0] <= yT1_uid74_invPolyEval_b; + prodXY_uid87_pT1_uid75_invPolyEval_cma_c0[0] <= memoryC2_uid68_sqrtTables_lutmem_r; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid87_pT1_uid75_invPolyEval_cma_a1 <= '{default: '0}; + prodXY_uid87_pT1_uid75_invPolyEval_cma_c1 <= '{default: '0}; + end + else + begin + if (prodXY_uid87_pT1_uid75_invPolyEval_cma_ena2 == 1'b1) + begin + prodXY_uid87_pT1_uid75_invPolyEval_cma_a1 <= prodXY_uid87_pT1_uid75_invPolyEval_cma_a0; + prodXY_uid87_pT1_uid75_invPolyEval_cma_c1 <= prodXY_uid87_pT1_uid75_invPolyEval_cma_c0; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid87_pT1_uid75_invPolyEval_cma_s <= '{default: '0}; + end + else + begin + if (prodXY_uid87_pT1_uid75_invPolyEval_cma_ena1 == 1'b1) + begin + prodXY_uid87_pT1_uid75_invPolyEval_cma_s[0] <= prodXY_uid87_pT1_uid75_invPolyEval_cma_y[0]; + end + end + end + dspba_delay_ver #( .width(24), .depth(0), .reset_kind("ASYNC") ) + prodXY_uid87_pT1_uid75_invPolyEval_cma_delay ( .xin(prodXY_uid87_pT1_uid75_invPolyEval_cma_s[0][23:0]), .xout(prodXY_uid87_pT1_uid75_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign prodXY_uid87_pT1_uid75_invPolyEval_cma_q = prodXY_uid87_pT1_uid75_invPolyEval_cma_qq[23:0]; + + // osig_uid88_pT1_uid75_invPolyEval(BITSELECT,87)@5 + assign osig_uid88_pT1_uid75_invPolyEval_b = prodXY_uid87_pT1_uid75_invPolyEval_cma_q[23:11]; + + // highBBits_uid77_invPolyEval(BITSELECT,76)@5 + assign highBBits_uid77_invPolyEval_b = osig_uid88_pT1_uid75_invPolyEval_b[12:1]; + + // redist7_yAddr_uid35_fpSqrtTest_b_3(DELAY,104) + dspba_delay_ver #( .width(8), .depth(3), .reset_kind("ASYNC") ) + redist7_yAddr_uid35_fpSqrtTest_b_3 ( .xin(yAddr_uid35_fpSqrtTest_b), .xout(redist7_yAddr_uid35_fpSqrtTest_b_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // memoryC1_uid65_sqrtTables_lutmem(DUALMEM,93)@3 + 2 + // in j@20000000 + assign memoryC1_uid65_sqrtTables_lutmem_aa = redist7_yAddr_uid35_fpSqrtTest_b_3_q; + assign memoryC1_uid65_sqrtTables_lutmem_reset0 = areset; + altera_syncram #( + .ram_block_type("M20K"), + .operation_mode("ROM"), + .width_a(21), + .widthad_a(8), + .numwords_a(256), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .outdata_reg_a("CLOCK0"), + .outdata_aclr_a("CLEAR0"), + .clock_enable_input_a("NORMAL"), + .power_up_uninitialized("FALSE"), + .init_file("acl_fp_sqrt_memoryC1_uid65_sqrtTables_lutmem.hex"), + .init_file_layout("PORT_A"), + .intended_device_family("Arria 10") + ) memoryC1_uid65_sqrtTables_lutmem_dmem ( + .clocken0(en[0]), + .aclr0(memoryC1_uid65_sqrtTables_lutmem_reset0), + .clock0(clk), + .address_a(memoryC1_uid65_sqrtTables_lutmem_aa), + .q_a(memoryC1_uid65_sqrtTables_lutmem_ir), + .wren_a(), + .wren_b(), + .rden_a(), + .rden_b(), + .data_a(), + .data_b(), + .address_b(), + .clock1(), + .clocken1(), + .clocken2(), + .clocken3(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_b(), + .eccstatus() + ); + assign memoryC1_uid65_sqrtTables_lutmem_r = memoryC1_uid65_sqrtTables_lutmem_ir[20:0]; + + // s1sumAHighB_uid78_invPolyEval(ADD,77)@5 + 1 + assign s1sumAHighB_uid78_invPolyEval_a = {{1{memoryC1_uid65_sqrtTables_lutmem_r[20]}}, memoryC1_uid65_sqrtTables_lutmem_r}; + assign s1sumAHighB_uid78_invPolyEval_b = {{10{highBBits_uid77_invPolyEval_b[11]}}, highBBits_uid77_invPolyEval_b}; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + s1sumAHighB_uid78_invPolyEval_o <= 22'b0; + end + else if (en == 1'b1) + begin + s1sumAHighB_uid78_invPolyEval_o <= $signed(s1sumAHighB_uid78_invPolyEval_a) + $signed(s1sumAHighB_uid78_invPolyEval_b); + end + end + assign s1sumAHighB_uid78_invPolyEval_q = s1sumAHighB_uid78_invPolyEval_o[21:0]; + + // lowRangeB_uid76_invPolyEval(BITSELECT,75)@5 + assign lowRangeB_uid76_invPolyEval_in = osig_uid88_pT1_uid75_invPolyEval_b[0:0]; + assign lowRangeB_uid76_invPolyEval_b = lowRangeB_uid76_invPolyEval_in[0:0]; + + // redist0_lowRangeB_uid76_invPolyEval_b_1(DELAY,97) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist0_lowRangeB_uid76_invPolyEval_b_1 ( .xin(lowRangeB_uid76_invPolyEval_b), .xout(redist0_lowRangeB_uid76_invPolyEval_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // s1_uid79_invPolyEval(BITJOIN,78)@6 + assign s1_uid79_invPolyEval_q = {s1sumAHighB_uid78_invPolyEval_q, redist0_lowRangeB_uid76_invPolyEval_b_1_q}; + + // redist6_yForPe_uid36_fpSqrtTest_b_6_notEnable(LOGICAL,115) + assign redist6_yForPe_uid36_fpSqrtTest_b_6_notEnable_q = ~ (en); + + // redist6_yForPe_uid36_fpSqrtTest_b_6_nor(LOGICAL,116) + assign redist6_yForPe_uid36_fpSqrtTest_b_6_nor_q = ~ (redist6_yForPe_uid36_fpSqrtTest_b_6_notEnable_q | redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena_q); + + // redist6_yForPe_uid36_fpSqrtTest_b_6_mem_last(CONSTANT,112) + assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_last_q = 2'b01; + + // redist6_yForPe_uid36_fpSqrtTest_b_6_cmp(LOGICAL,113) + assign redist6_yForPe_uid36_fpSqrtTest_b_6_cmp_q = redist6_yForPe_uid36_fpSqrtTest_b_6_mem_last_q == redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q ? 1'b1 : 1'b0; + + // redist6_yForPe_uid36_fpSqrtTest_b_6_cmpReg(REG,114) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist6_yForPe_uid36_fpSqrtTest_b_6_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist6_yForPe_uid36_fpSqrtTest_b_6_cmpReg_q <= redist6_yForPe_uid36_fpSqrtTest_b_6_cmp_q; + end + end + + // redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena(REG,117) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena_q <= 1'b0; + end + else if (redist6_yForPe_uid36_fpSqrtTest_b_6_nor_q == 1'b1) + begin + redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena_q <= redist6_yForPe_uid36_fpSqrtTest_b_6_cmpReg_q; + end + end + + // redist6_yForPe_uid36_fpSqrtTest_b_6_enaAnd(LOGICAL,118) + assign redist6_yForPe_uid36_fpSqrtTest_b_6_enaAnd_q = redist6_yForPe_uid36_fpSqrtTest_b_6_sticky_ena_q & en; + + // redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt(COUNTER,109) + // low=0, high=2, step=1, init=0 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i <= 2'd0; + redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i == 2'd1) + begin + redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_eq <= 1'b1; + end + else + begin + redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_eq <= 1'b0; + end + if (redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_eq == 1'b1) + begin + redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i <= $unsigned(redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i) + $unsigned(2'd2); + end + else + begin + redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i <= $unsigned(redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i) + $unsigned(2'd1); + end + end + end + assign redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_q = redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_i[1:0]; + + // redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux(MUX,110) + assign redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_s = en; + always @(redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_s or redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q or redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_q) + begin + unique case (redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_s) + 1'b0 : redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q = redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q; + 1'b1 : redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q = redist6_yForPe_uid36_fpSqrtTest_b_6_rdcnt_q; + default : redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q = 2'b0; + endcase + end + + // VCC(CONSTANT,1) + assign VCC_q = 1'b1; + + // redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr(REG,111) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q <= 2'b10; + end + else + begin + redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q <= redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q; + end + end + + // redist6_yForPe_uid36_fpSqrtTest_b_6_mem(DUALMEM,108) + assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ia = redist5_yForPe_uid36_fpSqrtTest_b_2_q; + assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_aa = redist6_yForPe_uid36_fpSqrtTest_b_6_wraddr_q; + assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ab = redist6_yForPe_uid36_fpSqrtTest_b_6_rdmux_q; + assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(16), + .widthad_a(2), + .numwords_a(3), + .width_b(16), + .widthad_b(2), + .numwords_b(3), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_aclr_b("CLEAR1"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Arria 10") + ) redist6_yForPe_uid36_fpSqrtTest_b_6_mem_dmem ( + .clocken1(redist6_yForPe_uid36_fpSqrtTest_b_6_enaAnd_q[0]), + .clocken0(VCC_q[0]), + .clock0(clk), + .aclr1(redist6_yForPe_uid36_fpSqrtTest_b_6_mem_reset0), + .clock1(clk), + .address_a(redist6_yForPe_uid36_fpSqrtTest_b_6_mem_aa), + .data_a(redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ia), + .wren_a(en[0]), + .address_b(redist6_yForPe_uid36_fpSqrtTest_b_6_mem_ab), + .q_b(redist6_yForPe_uid36_fpSqrtTest_b_6_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist6_yForPe_uid36_fpSqrtTest_b_6_mem_q = redist6_yForPe_uid36_fpSqrtTest_b_6_mem_iq[15:0]; + + // GND(CONSTANT,0) + assign GND_q = 1'b0; + + // prodXY_uid90_pT2_uid81_invPolyEval_cma(CHAINMULTADD,96)@6 + 3 + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_reset = areset; + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_ena0 = en[0]; + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_ena1 = prodXY_uid90_pT2_uid81_invPolyEval_cma_ena0; + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_ena2 = prodXY_uid90_pT2_uid81_invPolyEval_cma_ena0; + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_l[0] = $signed({1'b0, prodXY_uid90_pT2_uid81_invPolyEval_cma_a1[0][15:0]}); + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_p[0] = prodXY_uid90_pT2_uid81_invPolyEval_cma_l[0] * prodXY_uid90_pT2_uid81_invPolyEval_cma_c1[0]; + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_u[0] = prodXY_uid90_pT2_uid81_invPolyEval_cma_p[0][39:0]; + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_w[0] = prodXY_uid90_pT2_uid81_invPolyEval_cma_u[0]; + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_x[0] = prodXY_uid90_pT2_uid81_invPolyEval_cma_w[0]; + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_y[0] = prodXY_uid90_pT2_uid81_invPolyEval_cma_x[0]; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid90_pT2_uid81_invPolyEval_cma_a0 <= '{default: '0}; + prodXY_uid90_pT2_uid81_invPolyEval_cma_c0 <= '{default: '0}; + end + else + begin + if (prodXY_uid90_pT2_uid81_invPolyEval_cma_ena0 == 1'b1) + begin + prodXY_uid90_pT2_uid81_invPolyEval_cma_a0[0] <= redist6_yForPe_uid36_fpSqrtTest_b_6_mem_q; + prodXY_uid90_pT2_uid81_invPolyEval_cma_c0[0] <= s1_uid79_invPolyEval_q; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid90_pT2_uid81_invPolyEval_cma_a1 <= '{default: '0}; + prodXY_uid90_pT2_uid81_invPolyEval_cma_c1 <= '{default: '0}; + end + else + begin + if (prodXY_uid90_pT2_uid81_invPolyEval_cma_ena2 == 1'b1) + begin + prodXY_uid90_pT2_uid81_invPolyEval_cma_a1 <= prodXY_uid90_pT2_uid81_invPolyEval_cma_a0; + prodXY_uid90_pT2_uid81_invPolyEval_cma_c1 <= prodXY_uid90_pT2_uid81_invPolyEval_cma_c0; + end + end + end + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + prodXY_uid90_pT2_uid81_invPolyEval_cma_s <= '{default: '0}; + end + else + begin + if (prodXY_uid90_pT2_uid81_invPolyEval_cma_ena1 == 1'b1) + begin + prodXY_uid90_pT2_uid81_invPolyEval_cma_s[0] <= prodXY_uid90_pT2_uid81_invPolyEval_cma_y[0]; + end + end + end + dspba_delay_ver #( .width(39), .depth(0), .reset_kind("ASYNC") ) + prodXY_uid90_pT2_uid81_invPolyEval_cma_delay ( .xin(prodXY_uid90_pT2_uid81_invPolyEval_cma_s[0][38:0]), .xout(prodXY_uid90_pT2_uid81_invPolyEval_cma_qq), .ena(en[0]), .clk(clk), .aclr(areset) ); + assign prodXY_uid90_pT2_uid81_invPolyEval_cma_q = prodXY_uid90_pT2_uid81_invPolyEval_cma_qq[38:0]; + + // osig_uid91_pT2_uid81_invPolyEval(BITSELECT,90)@9 + assign osig_uid91_pT2_uid81_invPolyEval_b = prodXY_uid90_pT2_uid81_invPolyEval_cma_q[38:15]; + + // highBBits_uid83_invPolyEval(BITSELECT,82)@9 + assign highBBits_uid83_invPolyEval_b = osig_uid91_pT2_uid81_invPolyEval_b[23:2]; + + // redist8_yAddr_uid35_fpSqrtTest_b_7(DELAY,105) + dspba_delay_ver #( .width(8), .depth(4), .reset_kind("ASYNC") ) + redist8_yAddr_uid35_fpSqrtTest_b_7 ( .xin(redist7_yAddr_uid35_fpSqrtTest_b_3_q), .xout(redist8_yAddr_uid35_fpSqrtTest_b_7_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // memoryC0_uid62_sqrtTables_lutmem(DUALMEM,92)@7 + 2 + // in j@20000000 + assign memoryC0_uid62_sqrtTables_lutmem_aa = redist8_yAddr_uid35_fpSqrtTest_b_7_q; + assign memoryC0_uid62_sqrtTables_lutmem_reset0 = areset; + altera_syncram #( + .ram_block_type("M20K"), + .operation_mode("ROM"), + .width_a(29), + .widthad_a(8), + .numwords_a(256), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .outdata_reg_a("CLOCK0"), + .outdata_aclr_a("CLEAR0"), + .clock_enable_input_a("NORMAL"), + .power_up_uninitialized("FALSE"), + .init_file("acl_fp_sqrt_memoryC0_uid62_sqrtTables_lutmem.hex"), + .init_file_layout("PORT_A"), + .intended_device_family("Arria 10") + ) memoryC0_uid62_sqrtTables_lutmem_dmem ( + .clocken0(en[0]), + .aclr0(memoryC0_uid62_sqrtTables_lutmem_reset0), + .clock0(clk), + .address_a(memoryC0_uid62_sqrtTables_lutmem_aa), + .q_a(memoryC0_uid62_sqrtTables_lutmem_ir), + .wren_a(), + .wren_b(), + .rden_a(), + .rden_b(), + .data_a(), + .data_b(), + .address_b(), + .clock1(), + .clocken1(), + .clocken2(), + .clocken3(), + .aclr1(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_b(), + .eccstatus() + ); + assign memoryC0_uid62_sqrtTables_lutmem_r = memoryC0_uid62_sqrtTables_lutmem_ir[28:0]; + + // s2sumAHighB_uid84_invPolyEval(ADD,83)@9 + assign s2sumAHighB_uid84_invPolyEval_a = {{1{memoryC0_uid62_sqrtTables_lutmem_r[28]}}, memoryC0_uid62_sqrtTables_lutmem_r}; + assign s2sumAHighB_uid84_invPolyEval_b = {{8{highBBits_uid83_invPolyEval_b[21]}}, highBBits_uid83_invPolyEval_b}; + assign s2sumAHighB_uid84_invPolyEval_o = $signed(s2sumAHighB_uid84_invPolyEval_a) + $signed(s2sumAHighB_uid84_invPolyEval_b); + assign s2sumAHighB_uid84_invPolyEval_q = s2sumAHighB_uid84_invPolyEval_o[29:0]; + + // lowRangeB_uid82_invPolyEval(BITSELECT,81)@9 + assign lowRangeB_uid82_invPolyEval_in = osig_uid91_pT2_uid81_invPolyEval_b[1:0]; + assign lowRangeB_uid82_invPolyEval_b = lowRangeB_uid82_invPolyEval_in[1:0]; + + // s2_uid85_invPolyEval(BITJOIN,84)@9 + assign s2_uid85_invPolyEval_q = {s2sumAHighB_uid84_invPolyEval_q, lowRangeB_uid82_invPolyEval_b}; + + // expInc_uid38_fpSqrtTest(BITSELECT,37)@9 + assign expInc_uid38_fpSqrtTest_in = s2_uid85_invPolyEval_q[30:0]; + assign expInc_uid38_fpSqrtTest_b = expInc_uid38_fpSqrtTest_in[30:30]; + + // redist4_expInc_uid38_fpSqrtTest_b_1(DELAY,101) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist4_expInc_uid38_fpSqrtTest_b_1 ( .xin(expInc_uid38_fpSqrtTest_b), .xout(redist4_expInc_uid38_fpSqrtTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist9_expRMux_uid31_fpSqrtTest_q_10_notEnable(LOGICAL,127) + assign redist9_expRMux_uid31_fpSqrtTest_q_10_notEnable_q = ~ (en); + + // redist9_expRMux_uid31_fpSqrtTest_q_10_nor(LOGICAL,128) + assign redist9_expRMux_uid31_fpSqrtTest_q_10_nor_q = ~ (redist9_expRMux_uid31_fpSqrtTest_q_10_notEnable_q | redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena_q); + + // redist9_expRMux_uid31_fpSqrtTest_q_10_mem_last(CONSTANT,124) + assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_last_q = 4'b0101; + + // redist9_expRMux_uid31_fpSqrtTest_q_10_cmp(LOGICAL,125) + assign redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_b = {1'b0, redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q}; + assign redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_q = redist9_expRMux_uid31_fpSqrtTest_q_10_mem_last_q == redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_b ? 1'b1 : 1'b0; + + // redist9_expRMux_uid31_fpSqrtTest_q_10_cmpReg(REG,126) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_cmpReg_q <= 1'b0; + end + else if (en == 1'b1) + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_cmpReg_q <= redist9_expRMux_uid31_fpSqrtTest_q_10_cmp_q; + end + end + + // redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena(REG,129) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena_q <= 1'b0; + end + else if (redist9_expRMux_uid31_fpSqrtTest_q_10_nor_q == 1'b1) + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena_q <= redist9_expRMux_uid31_fpSqrtTest_q_10_cmpReg_q; + end + end + + // redist9_expRMux_uid31_fpSqrtTest_q_10_enaAnd(LOGICAL,130) + assign redist9_expRMux_uid31_fpSqrtTest_q_10_enaAnd_q = redist9_expRMux_uid31_fpSqrtTest_q_10_sticky_ena_q & en; + + // redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt(COUNTER,121) + // low=0, high=6, step=1, init=0 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i <= 3'd0; + redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_eq <= 1'b0; + end + else if (en == 1'b1) + begin + if (redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i == 3'd5) + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_eq <= 1'b1; + end + else + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_eq <= 1'b0; + end + if (redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_eq == 1'b1) + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i <= $unsigned(redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i) + $unsigned(3'd2); + end + else + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i <= $unsigned(redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i) + $unsigned(3'd1); + end + end + end + assign redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_q = redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_i[2:0]; + + // redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux(MUX,122) + assign redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_s = en; + always @(redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_s or redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q or redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_q) + begin + unique case (redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_s) + 1'b0 : redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q = redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q; + 1'b1 : redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q = redist9_expRMux_uid31_fpSqrtTest_q_10_rdcnt_q; + default : redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q = 3'b0; + endcase + end + + // sBiasM1_uid26_fpSqrtTest(CONSTANT,25) + assign sBiasM1_uid26_fpSqrtTest_q = 8'b01111110; + + // expOddSig_uid27_fpSqrtTest(ADD,26)@0 + assign expOddSig_uid27_fpSqrtTest_a = {1'b0, expX_uid6_fpSqrtTest_b}; + assign expOddSig_uid27_fpSqrtTest_b = {1'b0, sBiasM1_uid26_fpSqrtTest_q}; + assign expOddSig_uid27_fpSqrtTest_o = $unsigned(expOddSig_uid27_fpSqrtTest_a) + $unsigned(expOddSig_uid27_fpSqrtTest_b); + assign expOddSig_uid27_fpSqrtTest_q = expOddSig_uid27_fpSqrtTest_o[8:0]; + + // expROdd_uid28_fpSqrtTest(BITSELECT,27)@0 + assign expROdd_uid28_fpSqrtTest_b = expOddSig_uid27_fpSqrtTest_q[8:1]; + + // sBias_uid22_fpSqrtTest(CONSTANT,21) + assign sBias_uid22_fpSqrtTest_q = 8'b01111111; + + // expEvenSig_uid24_fpSqrtTest(ADD,23)@0 + assign expEvenSig_uid24_fpSqrtTest_a = {1'b0, expX_uid6_fpSqrtTest_b}; + assign expEvenSig_uid24_fpSqrtTest_b = {1'b0, sBias_uid22_fpSqrtTest_q}; + assign expEvenSig_uid24_fpSqrtTest_o = $unsigned(expEvenSig_uid24_fpSqrtTest_a) + $unsigned(expEvenSig_uid24_fpSqrtTest_b); + assign expEvenSig_uid24_fpSqrtTest_q = expEvenSig_uid24_fpSqrtTest_o[8:0]; + + // expREven_uid25_fpSqrtTest(BITSELECT,24)@0 + assign expREven_uid25_fpSqrtTest_b = expEvenSig_uid24_fpSqrtTest_q[8:1]; + + // expRMux_uid31_fpSqrtTest(MUX,30)@0 + 1 + assign expRMux_uid31_fpSqrtTest_s = expOddSelect_uid30_fpSqrtTest_q; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + expRMux_uid31_fpSqrtTest_q <= 8'b0; + end + else if (en == 1'b1) + begin + unique case (expRMux_uid31_fpSqrtTest_s) + 1'b0 : expRMux_uid31_fpSqrtTest_q <= expREven_uid25_fpSqrtTest_b; + 1'b1 : expRMux_uid31_fpSqrtTest_q <= expROdd_uid28_fpSqrtTest_b; + default : expRMux_uid31_fpSqrtTest_q <= 8'b0; + endcase + end + end + + // redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr(REG,123) + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q <= 3'b110; + end + else + begin + redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q <= redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q; + end + end + + // redist9_expRMux_uid31_fpSqrtTest_q_10_mem(DUALMEM,120) + assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ia = expRMux_uid31_fpSqrtTest_q; + assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_aa = redist9_expRMux_uid31_fpSqrtTest_q_10_wraddr_q; + assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ab = redist9_expRMux_uid31_fpSqrtTest_q_10_rdmux_q; + assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_reset0 = areset; + altera_syncram #( + .ram_block_type("MLAB"), + .operation_mode("DUAL_PORT"), + .width_a(8), + .widthad_a(3), + .numwords_a(7), + .width_b(8), + .widthad_b(3), + .numwords_b(7), + .lpm_type("altera_syncram"), + .width_byteena_a(1), + .address_reg_b("CLOCK0"), + .indata_reg_b("CLOCK0"), + .rdcontrol_reg_b("CLOCK0"), + .byteena_reg_b("CLOCK0"), + .outdata_reg_b("CLOCK1"), + .outdata_aclr_b("CLEAR1"), + .clock_enable_input_a("NORMAL"), + .clock_enable_input_b("NORMAL"), + .clock_enable_output_b("NORMAL"), + .read_during_write_mode_mixed_ports("DONT_CARE"), + .power_up_uninitialized("TRUE"), + .intended_device_family("Arria 10") + ) redist9_expRMux_uid31_fpSqrtTest_q_10_mem_dmem ( + .clocken1(redist9_expRMux_uid31_fpSqrtTest_q_10_enaAnd_q[0]), + .clocken0(VCC_q[0]), + .clock0(clk), + .aclr1(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_reset0), + .clock1(clk), + .address_a(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_aa), + .data_a(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ia), + .wren_a(en[0]), + .address_b(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_ab), + .q_b(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_iq), + .wren_b(), + .rden_a(), + .rden_b(), + .data_b(), + .clocken2(), + .clocken3(), + .aclr0(), + .addressstall_a(), + .addressstall_b(), + .byteena_a(), + .byteena_b(), + .eccencbypass(), + .eccencparity(), + .sclr(), + .address2_a(), + .address2_b(), + .q_a(), + .eccstatus() + ); + assign redist9_expRMux_uid31_fpSqrtTest_q_10_mem_q = redist9_expRMux_uid31_fpSqrtTest_q_10_mem_iq[7:0]; + + // redist9_expRMux_uid31_fpSqrtTest_q_10_outputreg(DELAY,119) + dspba_delay_ver #( .width(8), .depth(1), .reset_kind("ASYNC") ) + redist9_expRMux_uid31_fpSqrtTest_q_10_outputreg ( .xin(redist9_expRMux_uid31_fpSqrtTest_q_10_mem_q), .xout(redist9_expRMux_uid31_fpSqrtTest_q_10_outputreg_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expR_uid40_fpSqrtTest(ADD,39)@10 + assign expR_uid40_fpSqrtTest_a = {1'b0, redist9_expRMux_uid31_fpSqrtTest_q_10_outputreg_q}; + assign expR_uid40_fpSqrtTest_b = {8'b00000000, redist4_expInc_uid38_fpSqrtTest_b_1_q}; + assign expR_uid40_fpSqrtTest_o = $unsigned(expR_uid40_fpSqrtTest_a) + $unsigned(expR_uid40_fpSqrtTest_b); + assign expR_uid40_fpSqrtTest_q = expR_uid40_fpSqrtTest_o[8:0]; + + // expRR_uid51_fpSqrtTest(BITSELECT,50)@10 + assign expRR_uid51_fpSqrtTest_in = expR_uid40_fpSqrtTest_q[7:0]; + assign expRR_uid51_fpSqrtTest_b = expRR_uid51_fpSqrtTest_in[7:0]; + + // expXIsMax_uid14_fpSqrtTest(LOGICAL,13)@0 + 1 + assign expXIsMax_uid14_fpSqrtTest_qi = expX_uid6_fpSqrtTest_b == cstAllOWE_uid8_fpSqrtTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + expXIsMax_uid14_fpSqrtTest_delay ( .xin(expXIsMax_uid14_fpSqrtTest_qi), .xout(expXIsMax_uid14_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // invExpXIsMax_uid19_fpSqrtTest(LOGICAL,18)@1 + assign invExpXIsMax_uid19_fpSqrtTest_q = ~ (expXIsMax_uid14_fpSqrtTest_q); + + // InvExpXIsZero_uid20_fpSqrtTest(LOGICAL,19)@1 + assign InvExpXIsZero_uid20_fpSqrtTest_q = ~ (excZ_x_uid13_fpSqrtTest_q); + + // excR_x_uid21_fpSqrtTest(LOGICAL,20)@1 + assign excR_x_uid21_fpSqrtTest_q = InvExpXIsZero_uid20_fpSqrtTest_q & invExpXIsMax_uid19_fpSqrtTest_q; + + // minReg_uid43_fpSqrtTest(LOGICAL,42)@1 + assign minReg_uid43_fpSqrtTest_q = excR_x_uid21_fpSqrtTest_q & redist10_signX_uid7_fpSqrtTest_b_1_q; + + // cstZeroWF_uid9_fpSqrtTest(CONSTANT,8) + assign cstZeroWF_uid9_fpSqrtTest_q = 23'b00000000000000000000000; + + // fracXIsZero_uid15_fpSqrtTest(LOGICAL,14)@0 + 1 + assign fracXIsZero_uid15_fpSqrtTest_qi = cstZeroWF_uid9_fpSqrtTest_q == frac_x_uid12_fpSqrtTest_b ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + fracXIsZero_uid15_fpSqrtTest_delay ( .xin(fracXIsZero_uid15_fpSqrtTest_qi), .xout(fracXIsZero_uid15_fpSqrtTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excI_x_uid17_fpSqrtTest(LOGICAL,16)@1 + assign excI_x_uid17_fpSqrtTest_q = expXIsMax_uid14_fpSqrtTest_q & fracXIsZero_uid15_fpSqrtTest_q; + + // minInf_uid44_fpSqrtTest(LOGICAL,43)@1 + assign minInf_uid44_fpSqrtTest_q = excI_x_uid17_fpSqrtTest_q & redist10_signX_uid7_fpSqrtTest_b_1_q; + + // fracXIsNotZero_uid16_fpSqrtTest(LOGICAL,15)@1 + assign fracXIsNotZero_uid16_fpSqrtTest_q = ~ (fracXIsZero_uid15_fpSqrtTest_q); + + // excN_x_uid18_fpSqrtTest(LOGICAL,17)@1 + assign excN_x_uid18_fpSqrtTest_q = expXIsMax_uid14_fpSqrtTest_q & fracXIsNotZero_uid16_fpSqrtTest_q; + + // excRNaN_uid45_fpSqrtTest(LOGICAL,44)@1 + assign excRNaN_uid45_fpSqrtTest_q = excN_x_uid18_fpSqrtTest_q | minInf_uid44_fpSqrtTest_q | minReg_uid43_fpSqrtTest_q; + + // invSignX_uid41_fpSqrtTest(LOGICAL,40)@1 + assign invSignX_uid41_fpSqrtTest_q = ~ (redist10_signX_uid7_fpSqrtTest_b_1_q); + + // inInfAndNotNeg_uid42_fpSqrtTest(LOGICAL,41)@1 + assign inInfAndNotNeg_uid42_fpSqrtTest_q = excI_x_uid17_fpSqrtTest_q & invSignX_uid41_fpSqrtTest_q; + + // excConc_uid46_fpSqrtTest(BITJOIN,45)@1 + assign excConc_uid46_fpSqrtTest_q = {excRNaN_uid45_fpSqrtTest_q, inInfAndNotNeg_uid42_fpSqrtTest_q, excZ_x_uid13_fpSqrtTest_q}; + + // fracSelIn_uid47_fpSqrtTest(BITJOIN,46)@1 + assign fracSelIn_uid47_fpSqrtTest_q = {redist10_signX_uid7_fpSqrtTest_b_1_q, excConc_uid46_fpSqrtTest_q}; + + // fracSel_uid48_fpSqrtTest(LOOKUP,47)@1 + 1 + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + fracSel_uid48_fpSqrtTest_q <= 2'b01; + end + else if (en == 1'b1) + begin + unique case (fracSelIn_uid47_fpSqrtTest_q) + 4'b0000 : fracSel_uid48_fpSqrtTest_q <= 2'b01; + 4'b0001 : fracSel_uid48_fpSqrtTest_q <= 2'b00; + 4'b0010 : fracSel_uid48_fpSqrtTest_q <= 2'b10; + 4'b0011 : fracSel_uid48_fpSqrtTest_q <= 2'b00; + 4'b0100 : fracSel_uid48_fpSqrtTest_q <= 2'b11; + 4'b0101 : fracSel_uid48_fpSqrtTest_q <= 2'b00; + 4'b0110 : fracSel_uid48_fpSqrtTest_q <= 2'b10; + 4'b0111 : fracSel_uid48_fpSqrtTest_q <= 2'b00; + 4'b1000 : fracSel_uid48_fpSqrtTest_q <= 2'b11; + 4'b1001 : fracSel_uid48_fpSqrtTest_q <= 2'b00; + 4'b1010 : fracSel_uid48_fpSqrtTest_q <= 2'b11; + 4'b1011 : fracSel_uid48_fpSqrtTest_q <= 2'b11; + 4'b1100 : fracSel_uid48_fpSqrtTest_q <= 2'b11; + 4'b1101 : fracSel_uid48_fpSqrtTest_q <= 2'b11; + 4'b1110 : fracSel_uid48_fpSqrtTest_q <= 2'b11; + 4'b1111 : fracSel_uid48_fpSqrtTest_q <= 2'b11; + default : begin + // unreachable + fracSel_uid48_fpSqrtTest_q <= 2'bxx; + end + endcase + end + end + + // redist2_fracSel_uid48_fpSqrtTest_q_9(DELAY,99) + dspba_delay_ver #( .width(2), .depth(8), .reset_kind("ASYNC") ) + redist2_fracSel_uid48_fpSqrtTest_q_9 ( .xin(fracSel_uid48_fpSqrtTest_q), .xout(redist2_fracSel_uid48_fpSqrtTest_q_9_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expRPostExc_uid53_fpSqrtTest(MUX,52)@10 + assign expRPostExc_uid53_fpSqrtTest_s = redist2_fracSel_uid48_fpSqrtTest_q_9_q; + always @(expRPostExc_uid53_fpSqrtTest_s or en or cstAllZWE_uid10_fpSqrtTest_q or expRR_uid51_fpSqrtTest_b or cstAllOWE_uid8_fpSqrtTest_q) + begin + unique case (expRPostExc_uid53_fpSqrtTest_s) + 2'b00 : expRPostExc_uid53_fpSqrtTest_q = cstAllZWE_uid10_fpSqrtTest_q; + 2'b01 : expRPostExc_uid53_fpSqrtTest_q = expRR_uid51_fpSqrtTest_b; + 2'b10 : expRPostExc_uid53_fpSqrtTest_q = cstAllOWE_uid8_fpSqrtTest_q; + 2'b11 : expRPostExc_uid53_fpSqrtTest_q = cstAllOWE_uid8_fpSqrtTest_q; + default : expRPostExc_uid53_fpSqrtTest_q = 8'b0; + endcase + end + + // fracNaN_uid54_fpSqrtTest(CONSTANT,53) + assign fracNaN_uid54_fpSqrtTest_q = 23'b00000000000000000000001; + + // fracRPostProcessings_uid39_fpSqrtTest(BITSELECT,38)@9 + assign fracRPostProcessings_uid39_fpSqrtTest_in = s2_uid85_invPolyEval_q[28:0]; + assign fracRPostProcessings_uid39_fpSqrtTest_b = fracRPostProcessings_uid39_fpSqrtTest_in[28:6]; + + // redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1(DELAY,100) + dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) + redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1 ( .xin(fracRPostProcessings_uid39_fpSqrtTest_b), .xout(redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // fracRPostExc_uid58_fpSqrtTest(MUX,57)@10 + assign fracRPostExc_uid58_fpSqrtTest_s = redist2_fracSel_uid48_fpSqrtTest_q_9_q; + always @(fracRPostExc_uid58_fpSqrtTest_s or en or cstZeroWF_uid9_fpSqrtTest_q or redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1_q or fracNaN_uid54_fpSqrtTest_q) + begin + unique case (fracRPostExc_uid58_fpSqrtTest_s) + 2'b00 : fracRPostExc_uid58_fpSqrtTest_q = cstZeroWF_uid9_fpSqrtTest_q; + 2'b01 : fracRPostExc_uid58_fpSqrtTest_q = redist3_fracRPostProcessings_uid39_fpSqrtTest_b_1_q; + 2'b10 : fracRPostExc_uid58_fpSqrtTest_q = cstZeroWF_uid9_fpSqrtTest_q; + 2'b11 : fracRPostExc_uid58_fpSqrtTest_q = fracNaN_uid54_fpSqrtTest_q; + default : fracRPostExc_uid58_fpSqrtTest_q = 23'b0; + endcase + end + + // RSqrt_uid60_fpSqrtTest(BITJOIN,59)@10 + assign RSqrt_uid60_fpSqrtTest_q = {redist1_negZero_uid59_fpSqrtTest_q_9_q, expRPostExc_uid53_fpSqrtTest_q, fracRPostExc_uid58_fpSqrtTest_q}; + + // xOut(GPOUT,4)@10 + assign q = RSqrt_uid60_fpSqrtTest_q; + +endmodule diff --git a/hw/rtl/fp_cores/altera/acl_fp_sqrt_memoryC0_uid62_sqrtTables_lutmem.hex b/hw/rtl/fp_cores/altera/acl_fp_sqrt_memoryC0_uid62_sqrtTables_lutmem.hex new file mode 100644 index 00000000..dacc8b55 --- /dev/null +++ b/hw/rtl/fp_cores/altera/acl_fp_sqrt_memoryC0_uid62_sqrtTables_lutmem.hex @@ -0,0 +1,258 @@ +:020000040000FA +:0400000008000004F0 +:040001000807FC08E8 +:04000200080FF024CF +:040003000817DC6F8F +:04000400081FC0FF12 +:0400050008279DEC3F +:04000600082F734C00 +:040007000837413342 +:04000800083F07B7EF +:040009000846C6EEF1 +:04000A00084E7EEB33 +:04000B0008562FC2A2 +:04000C00085DD9882A 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+:0200F4000DDC21 +:0200F5000DDC20 +:0200F6000DDE1D +:0200F7000DE416 +:0200F8000DEC0D +:0200F9000DEC0C +:0200FA000DEE09 +:0200FB000DF600 +:0200FC000DF401 +:0200FD000DF6FE +:0200FE000DF8FB +:0200FF000E02EF +:00000001ff diff --git a/hw/rtl/fp_cores/altera/acl_fp_sub.v b/hw/rtl/fp_cores/altera/acl_fp_sub.v deleted file mode 100644 index f3a1956a..00000000 --- a/hw/rtl/fp_cores/altera/acl_fp_sub.v +++ /dev/null @@ -1,67 +0,0 @@ -// (C) 1992-2016 Intel Corporation. -// Intel, the Intel logo, Intel, MegaCore, NIOS II, Quartus and TalkBack words -// and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. -// and/or other countries. Other marks and brands may be claimed as the property -// of others. See Trademarks on intel.com for full list of Intel trademarks or -// the Trademarks & Brands Names Database (if Intel) or See www.Intel.com/legal (if Altera) -// Your use of Intel Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Intel MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Intel and sold by -// Intel or its authorized distributors. Please refer to the applicable -// agreement for further details. - -module acl_fp_add(dataa, datab, clock, enable, result); - -input [31:0] dataa; -input [31:0] datab; -input clock, enable; - -output [31:0] result; - -// FP MAC wysiwyg -twentynm_fp_mac mac_fp_wys ( - // inputs - .accumulate(), - .chainin_overflow(), - .chainin_invalid(), - .chainin_underflow(), - .chainin_inexact(), - .ax(dataa), - .ay(datab), - .az(), - .clk({2'b00,clock}), - .ena({2'b11,enable}), - .aclr(2'b00), - .chainin(), - // outputs - .overflow(), - .invalid(), - .underflow(), - .inexact(), - .chainout_overflow(), - .chainout_invalid(), - .chainout_underflow(), - .chainout_inexact(), - .resulta(result), - .chainout() -); -defparam mac_fp_wys.operation_mode = "sp_add"; -defparam mac_fp_wys.use_chainin = "false"; -defparam mac_fp_wys.adder_subtract = "true"; -defparam mac_fp_wys.ax_clock = "0"; -defparam mac_fp_wys.ay_clock = "0"; -defparam mac_fp_wys.az_clock = "none"; -defparam mac_fp_wys.output_clock = "0"; -defparam mac_fp_wys.accumulate_clock = "none"; -defparam mac_fp_wys.ax_chainin_pl_clock = "none"; -defparam mac_fp_wys.accum_pipeline_clock = "none"; -defparam mac_fp_wys.mult_pipeline_clock = "none"; -defparam mac_fp_wys.adder_input_clock = "0"; -defparam mac_fp_wys.accum_adder_clock = "none"; - -endmodule diff --git a/hw/rtl/fp_cores/altera/acl_fp_utof.sv b/hw/rtl/fp_cores/altera/acl_fp_utof.sv new file mode 100644 index 00000000..2ba2b67d --- /dev/null +++ b/hw/rtl/fp_cores/altera/acl_fp_utof.sv @@ -0,0 +1,486 @@ +// ------------------------------------------------------------------------- +// High Level Design Compiler for Intel(R) FPGAs Version 17.1 (Release Build #273) +// Quartus Prime development tool and MATLAB/Simulink Interface +// +// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly +// subject to the terms and conditions of the Intel FPGA Software License +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by Intel +// and sold by Intel or its authorized distributors. Please refer to the +// applicable agreement for further details. +// --------------------------------------------------------------------------- + +// SystemVerilog created from acl_fp_utof +// SystemVerilog created on Wed Aug 5 12:58:16 2020 + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *) +module acl_fp_utof ( + input wire [31:0] a, + input wire [0:0] en, + output wire [31:0] q, + input wire clk, + input wire areset + ); + + wire [0:0] GND_q; + wire [5:0] maxCount_uid7_fxpToFPTest_q; + wire [0:0] inIsZero_uid8_fxpToFPTest_qi; + reg [0:0] inIsZero_uid8_fxpToFPTest_q; + wire [7:0] msbIn_uid9_fxpToFPTest_q; + wire [8:0] expPreRnd_uid10_fxpToFPTest_a; + wire [8:0] expPreRnd_uid10_fxpToFPTest_b; + logic [8:0] expPreRnd_uid10_fxpToFPTest_o; + wire [8:0] expPreRnd_uid10_fxpToFPTest_q; + wire [32:0] expFracRnd_uid12_fxpToFPTest_q; + wire [0:0] sticky_uid16_fxpToFPTest_qi; + reg [0:0] sticky_uid16_fxpToFPTest_q; + wire [0:0] nr_uid17_fxpToFPTest_q; + wire [0:0] rnd_uid18_fxpToFPTest_qi; + reg [0:0] rnd_uid18_fxpToFPTest_q; + wire [34:0] expFracR_uid20_fxpToFPTest_a; + wire [34:0] expFracR_uid20_fxpToFPTest_b; + logic [34:0] expFracR_uid20_fxpToFPTest_o; + wire [33:0] expFracR_uid20_fxpToFPTest_q; + wire [23:0] fracR_uid21_fxpToFPTest_in; + wire [22:0] fracR_uid21_fxpToFPTest_b; + wire [9:0] expR_uid22_fxpToFPTest_b; + wire [11:0] udf_uid23_fxpToFPTest_a; + wire [11:0] udf_uid23_fxpToFPTest_b; + logic [11:0] udf_uid23_fxpToFPTest_o; + wire [0:0] udf_uid23_fxpToFPTest_n; + wire [7:0] expInf_uid24_fxpToFPTest_q; + wire [11:0] ovf_uid25_fxpToFPTest_a; + wire [11:0] ovf_uid25_fxpToFPTest_b; + logic [11:0] ovf_uid25_fxpToFPTest_o; + wire [0:0] ovf_uid25_fxpToFPTest_n; + wire [0:0] excSelector_uid26_fxpToFPTest_q; + wire [22:0] fracZ_uid27_fxpToFPTest_q; + wire [0:0] fracRPostExc_uid28_fxpToFPTest_s; + reg [22:0] fracRPostExc_uid28_fxpToFPTest_q; + wire [0:0] udfOrInZero_uid29_fxpToFPTest_q; + wire [1:0] excSelector_uid30_fxpToFPTest_q; + wire [7:0] expZ_uid33_fxpToFPTest_q; + wire [7:0] expR_uid34_fxpToFPTest_in; + wire [7:0] expR_uid34_fxpToFPTest_b; + wire [1:0] expRPostExc_uid35_fxpToFPTest_s; + reg [7:0] expRPostExc_uid35_fxpToFPTest_q; + wire [31:0] outRes_uid36_fxpToFPTest_q; + wire [31:0] zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_qi; + reg [0:0] vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s; + reg [31:0] vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [15:0] zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [31:0] cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s; + reg [31:0] vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [31:0] cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s; + reg [31:0] vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [3:0] zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [31:0] cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s; + reg [31:0] vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [1:0] zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [31:0] cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s; + reg [31:0] vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [31:0] cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [0:0] vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s; + reg [31:0] vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [5:0] vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a; + wire [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b; + logic [7:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o; + wire [0:0] vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c; + wire [0:0] vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s; + reg [5:0] vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q; + wire [1:0] l_uid13_fxpToFPTest_merged_bit_select_in; + wire [0:0] l_uid13_fxpToFPTest_merged_bit_select_b; + wire [0:0] l_uid13_fxpToFPTest_merged_bit_select_c; + wire [15:0] rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b; + wire [15:0] rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c; + wire [7:0] rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b; + wire [23:0] rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c; + wire [3:0] rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b; + wire [27:0] rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c; + wire [1:0] rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b; + wire [29:0] rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c; + wire [0:0] rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b; + wire [30:0] rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c; + wire [30:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_in; + wire [23:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_b; + wire [6:0] fracRnd_uid11_fxpToFPTest_merged_bit_select_c; + reg [23:0] redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q; + reg [0:0] redist1_vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q_1_q; + reg [0:0] redist2_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q; + reg [0:0] redist3_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q; + reg [0:0] redist4_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q; + reg [0:0] redist5_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q; + reg [9:0] redist6_expR_uid22_fxpToFPTest_b_1_q; + reg [22:0] redist7_fracR_uid21_fxpToFPTest_b_1_q; + reg [32:0] redist8_expFracRnd_uid12_fxpToFPTest_q_1_q; + reg [0:0] redist9_inIsZero_uid8_fxpToFPTest_q_2_q; + reg [31:0] redist10_xIn_a_1_q; + + + // GND(CONSTANT,0) + assign GND_q = 1'b0; + + // expInf_uid24_fxpToFPTest(CONSTANT,23) + assign expInf_uid24_fxpToFPTest_q = 8'b11111111; + + // expZ_uid33_fxpToFPTest(CONSTANT,32) + assign expZ_uid33_fxpToFPTest_q = 8'b00000000; + + // rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,89)@4 + assign rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q[31:31]; + assign rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q[30:0]; + + // cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,75)@4 + assign cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, GND_q}; + + // rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,88)@3 + assign rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q[31:30]; + assign rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q[29:0]; + + // zs_uid64_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,63) + assign zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q = 2'b00; + + // cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,68)@3 + assign cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q}; + + // rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,87)@3 + assign rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q[31:28]; + assign rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q[27:0]; + + // zs_uid57_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,56) + assign zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q = 4'b0000; + + // cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,61)@3 + assign cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q}; + + // rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,86)@2 + assign rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q[31:24]; + assign rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q[23:0]; + + // cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,54)@2 + assign cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, expZ_uid33_fxpToFPTest_q}; + + // rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select(BITSELECT,85)@1 + assign rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b = vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q[31:16]; + assign rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c = vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q[15:0]; + + // zs_uid43_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,42) + assign zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q = 16'b0000000000000000; + + // cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,47)@1 + assign cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q = {rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_c, zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q}; + + // zs_uid38_lzcShifterZ1_uid6_fxpToFPTest(CONSTANT,37) + assign zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b00000000000000000000000000000000; + + // redist10_xIn_a_1(DELAY,101) + dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") ) + redist10_xIn_a_1 ( .xin(a), .xout(redist10_xIn_a_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,39)@0 + 1 + assign vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_qi = a == zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_delay ( .xin(vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_qi), .xout(vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest(MUX,41)@1 + assign vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q; + always @(vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s or en or redist10_xIn_a_1_q or zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q) + begin + unique case (vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_s) + 1'b0 : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q = redist10_xIn_a_1_q; + 1'b1 : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q = zs_uid38_lzcShifterZ1_uid6_fxpToFPTest_q; + default : vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b0; + endcase + end + + // vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,44)@1 + assign vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid44_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid43_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0; + + // vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest(MUX,48)@1 + 1 + assign vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; + end + else if (en == 1'b1) + begin + unique case (vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_s) + 1'b0 : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid42_lzcShifterZ1_uid6_fxpToFPTest_q; + 1'b1 : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid48_lzcShifterZ1_uid6_fxpToFPTest_q; + default : vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; + endcase + end + end + + // vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,51)@2 + assign vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid51_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == expZ_uid33_fxpToFPTest_q ? 1'b1 : 1'b0; + + // vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest(MUX,55)@2 + 1 + assign vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; + end + else if (en == 1'b1) + begin + unique case (vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_s) + 1'b0 : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid49_lzcShifterZ1_uid6_fxpToFPTest_q; + 1'b1 : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid55_lzcShifterZ1_uid6_fxpToFPTest_q; + default : vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; + endcase + end + end + + // vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,58)@3 + assign vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid58_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid57_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0; + + // vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest(MUX,62)@3 + assign vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q; + always @(vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s or en or vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q or cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q) + begin + unique case (vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_s) + 1'b0 : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q = vStagei_uid56_lzcShifterZ1_uid6_fxpToFPTest_q; + 1'b1 : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q = cStage_uid62_lzcShifterZ1_uid6_fxpToFPTest_q; + default : vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b0; + endcase + end + + // vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,65)@3 + assign vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid65_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == zs_uid64_lzcShifterZ1_uid6_fxpToFPTest_q ? 1'b1 : 1'b0; + + // vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest(MUX,69)@3 + 1 + assign vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; + end + else if (en == 1'b1) + begin + unique case (vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_s) + 1'b0 : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q <= vStagei_uid63_lzcShifterZ1_uid6_fxpToFPTest_q; + 1'b1 : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q <= cStage_uid69_lzcShifterZ1_uid6_fxpToFPTest_q; + default : vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q <= 32'b0; + endcase + end + end + + // vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest(LOGICAL,72)@4 + assign vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q = rVStage_uid72_lzcShifterZ1_uid6_fxpToFPTest_merged_bit_select_b == GND_q ? 1'b1 : 1'b0; + + // vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest(MUX,76)@4 + assign vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s = vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q; + always @(vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s or en or vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q or cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q) + begin + unique case (vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_s) + 1'b0 : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = vStagei_uid70_lzcShifterZ1_uid6_fxpToFPTest_q; + 1'b1 : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = cStage_uid76_lzcShifterZ1_uid6_fxpToFPTest_q; + default : vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q = 32'b0; + endcase + end + + // fracRnd_uid11_fxpToFPTest_merged_bit_select(BITSELECT,90)@4 + assign fracRnd_uid11_fxpToFPTest_merged_bit_select_in = vStagei_uid77_lzcShifterZ1_uid6_fxpToFPTest_q[30:0]; + assign fracRnd_uid11_fxpToFPTest_merged_bit_select_b = fracRnd_uid11_fxpToFPTest_merged_bit_select_in[30:7]; + assign fracRnd_uid11_fxpToFPTest_merged_bit_select_c = fracRnd_uid11_fxpToFPTest_merged_bit_select_in[6:0]; + + // sticky_uid16_fxpToFPTest(LOGICAL,15)@4 + 1 + assign sticky_uid16_fxpToFPTest_qi = fracRnd_uid11_fxpToFPTest_merged_bit_select_c != 7'b0000000 ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + sticky_uid16_fxpToFPTest_delay ( .xin(sticky_uid16_fxpToFPTest_qi), .xout(sticky_uid16_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // nr_uid17_fxpToFPTest(LOGICAL,16)@5 + assign nr_uid17_fxpToFPTest_q = ~ (l_uid13_fxpToFPTest_merged_bit_select_c); + + // maxCount_uid7_fxpToFPTest(CONSTANT,6) + assign maxCount_uid7_fxpToFPTest_q = 6'b100000; + + // redist5_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4(DELAY,96) + dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") ) + redist5_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4 ( .xin(vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q), .xout(redist5_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist4_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3(DELAY,95) + dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") ) + redist4_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3 ( .xin(vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q), .xout(redist4_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist3_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2(DELAY,94) + dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") ) + redist3_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2 ( .xin(vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q), .xout(redist3_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist2_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1(DELAY,93) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist2_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1 ( .xin(vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q), .xout(redist2_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist1_vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q_1(DELAY,92) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist1_vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q_1 ( .xin(vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q), .xout(redist1_vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest(BITJOIN,77)@4 + assign vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q = {redist5_vCount_uid40_lzcShifterZ1_uid6_fxpToFPTest_q_4_q, redist4_vCount_uid45_lzcShifterZ1_uid6_fxpToFPTest_q_3_q, redist3_vCount_uid52_lzcShifterZ1_uid6_fxpToFPTest_q_2_q, redist2_vCount_uid59_lzcShifterZ1_uid6_fxpToFPTest_q_1_q, redist1_vCount_uid66_lzcShifterZ1_uid6_fxpToFPTest_q_1_q, vCount_uid73_lzcShifterZ1_uid6_fxpToFPTest_q}; + + // vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest(COMPARE,79)@4 + assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a = {2'b00, maxCount_uid7_fxpToFPTest_q}; + assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b = {2'b00, vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q}; + assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o = $unsigned(vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_a) - $unsigned(vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_b); + assign vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c[0] = vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_o[7]; + + // vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest(MUX,81)@4 + 1 + assign vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s = vCountBig_uid80_lzcShifterZ1_uid6_fxpToFPTest_c; + always @ (posedge clk or posedge areset) + begin + if (areset) + begin + vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q <= 6'b0; + end + else if (en == 1'b1) + begin + unique case (vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_s) + 1'b0 : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q <= vCount_uid78_lzcShifterZ1_uid6_fxpToFPTest_q; + 1'b1 : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q <= maxCount_uid7_fxpToFPTest_q; + default : vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q <= 6'b0; + endcase + end + end + + // msbIn_uid9_fxpToFPTest(CONSTANT,8) + assign msbIn_uid9_fxpToFPTest_q = 8'b10011110; + + // expPreRnd_uid10_fxpToFPTest(SUB,9)@5 + assign expPreRnd_uid10_fxpToFPTest_a = {1'b0, msbIn_uid9_fxpToFPTest_q}; + assign expPreRnd_uid10_fxpToFPTest_b = {3'b000, vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q}; + assign expPreRnd_uid10_fxpToFPTest_o = $unsigned(expPreRnd_uid10_fxpToFPTest_a) - $unsigned(expPreRnd_uid10_fxpToFPTest_b); + assign expPreRnd_uid10_fxpToFPTest_q = expPreRnd_uid10_fxpToFPTest_o[8:0]; + + // redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1(DELAY,91) + dspba_delay_ver #( .width(24), .depth(1), .reset_kind("ASYNC") ) + redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1 ( .xin(fracRnd_uid11_fxpToFPTest_merged_bit_select_b), .xout(redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expFracRnd_uid12_fxpToFPTest(BITJOIN,11)@5 + assign expFracRnd_uid12_fxpToFPTest_q = {expPreRnd_uid10_fxpToFPTest_q, redist0_fracRnd_uid11_fxpToFPTest_merged_bit_select_b_1_q}; + + // l_uid13_fxpToFPTest_merged_bit_select(BITSELECT,84)@5 + assign l_uid13_fxpToFPTest_merged_bit_select_in = expFracRnd_uid12_fxpToFPTest_q[1:0]; + assign l_uid13_fxpToFPTest_merged_bit_select_b = l_uid13_fxpToFPTest_merged_bit_select_in[1:1]; + assign l_uid13_fxpToFPTest_merged_bit_select_c = l_uid13_fxpToFPTest_merged_bit_select_in[0:0]; + + // rnd_uid18_fxpToFPTest(LOGICAL,17)@5 + 1 + assign rnd_uid18_fxpToFPTest_qi = l_uid13_fxpToFPTest_merged_bit_select_b | nr_uid17_fxpToFPTest_q | sticky_uid16_fxpToFPTest_q; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + rnd_uid18_fxpToFPTest_delay ( .xin(rnd_uid18_fxpToFPTest_qi), .xout(rnd_uid18_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist8_expFracRnd_uid12_fxpToFPTest_q_1(DELAY,99) + dspba_delay_ver #( .width(33), .depth(1), .reset_kind("ASYNC") ) + redist8_expFracRnd_uid12_fxpToFPTest_q_1 ( .xin(expFracRnd_uid12_fxpToFPTest_q), .xout(redist8_expFracRnd_uid12_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expFracR_uid20_fxpToFPTest(ADD,19)@6 + assign expFracR_uid20_fxpToFPTest_a = {{2{redist8_expFracRnd_uid12_fxpToFPTest_q_1_q[32]}}, redist8_expFracRnd_uid12_fxpToFPTest_q_1_q}; + assign expFracR_uid20_fxpToFPTest_b = {34'b0000000000000000000000000000000000, rnd_uid18_fxpToFPTest_q}; + assign expFracR_uid20_fxpToFPTest_o = $signed(expFracR_uid20_fxpToFPTest_a) + $signed(expFracR_uid20_fxpToFPTest_b); + assign expFracR_uid20_fxpToFPTest_q = expFracR_uid20_fxpToFPTest_o[33:0]; + + // expR_uid22_fxpToFPTest(BITSELECT,21)@6 + assign expR_uid22_fxpToFPTest_b = expFracR_uid20_fxpToFPTest_q[33:24]; + + // redist6_expR_uid22_fxpToFPTest_b_1(DELAY,97) + dspba_delay_ver #( .width(10), .depth(1), .reset_kind("ASYNC") ) + redist6_expR_uid22_fxpToFPTest_b_1 ( .xin(expR_uid22_fxpToFPTest_b), .xout(redist6_expR_uid22_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // expR_uid34_fxpToFPTest(BITSELECT,33)@7 + assign expR_uid34_fxpToFPTest_in = redist6_expR_uid22_fxpToFPTest_b_1_q[7:0]; + assign expR_uid34_fxpToFPTest_b = expR_uid34_fxpToFPTest_in[7:0]; + + // ovf_uid25_fxpToFPTest(COMPARE,24)@7 + assign ovf_uid25_fxpToFPTest_a = {{2{redist6_expR_uid22_fxpToFPTest_b_1_q[9]}}, redist6_expR_uid22_fxpToFPTest_b_1_q}; + assign ovf_uid25_fxpToFPTest_b = {4'b0000, expInf_uid24_fxpToFPTest_q}; + assign ovf_uid25_fxpToFPTest_o = $signed(ovf_uid25_fxpToFPTest_a) - $signed(ovf_uid25_fxpToFPTest_b); + assign ovf_uid25_fxpToFPTest_n[0] = ~ (ovf_uid25_fxpToFPTest_o[11]); + + // inIsZero_uid8_fxpToFPTest(LOGICAL,7)@5 + 1 + assign inIsZero_uid8_fxpToFPTest_qi = vCountFinal_uid82_lzcShifterZ1_uid6_fxpToFPTest_q == maxCount_uid7_fxpToFPTest_q ? 1'b1 : 1'b0; + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + inIsZero_uid8_fxpToFPTest_delay ( .xin(inIsZero_uid8_fxpToFPTest_qi), .xout(inIsZero_uid8_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // redist9_inIsZero_uid8_fxpToFPTest_q_2(DELAY,100) + dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") ) + redist9_inIsZero_uid8_fxpToFPTest_q_2 ( .xin(inIsZero_uid8_fxpToFPTest_q), .xout(redist9_inIsZero_uid8_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // udf_uid23_fxpToFPTest(COMPARE,22)@7 + assign udf_uid23_fxpToFPTest_a = {11'b00000000000, GND_q}; + assign udf_uid23_fxpToFPTest_b = {{2{redist6_expR_uid22_fxpToFPTest_b_1_q[9]}}, redist6_expR_uid22_fxpToFPTest_b_1_q}; + assign udf_uid23_fxpToFPTest_o = $signed(udf_uid23_fxpToFPTest_a) - $signed(udf_uid23_fxpToFPTest_b); + assign udf_uid23_fxpToFPTest_n[0] = ~ (udf_uid23_fxpToFPTest_o[11]); + + // udfOrInZero_uid29_fxpToFPTest(LOGICAL,28)@7 + assign udfOrInZero_uid29_fxpToFPTest_q = udf_uid23_fxpToFPTest_n | redist9_inIsZero_uid8_fxpToFPTest_q_2_q; + + // excSelector_uid30_fxpToFPTest(BITJOIN,29)@7 + assign excSelector_uid30_fxpToFPTest_q = {ovf_uid25_fxpToFPTest_n, udfOrInZero_uid29_fxpToFPTest_q}; + + // expRPostExc_uid35_fxpToFPTest(MUX,34)@7 + assign expRPostExc_uid35_fxpToFPTest_s = excSelector_uid30_fxpToFPTest_q; + always @(expRPostExc_uid35_fxpToFPTest_s or en or expR_uid34_fxpToFPTest_b or expZ_uid33_fxpToFPTest_q or expInf_uid24_fxpToFPTest_q) + begin + unique case (expRPostExc_uid35_fxpToFPTest_s) + 2'b00 : expRPostExc_uid35_fxpToFPTest_q = expR_uid34_fxpToFPTest_b; + 2'b01 : expRPostExc_uid35_fxpToFPTest_q = expZ_uid33_fxpToFPTest_q; + 2'b10 : expRPostExc_uid35_fxpToFPTest_q = expInf_uid24_fxpToFPTest_q; + 2'b11 : expRPostExc_uid35_fxpToFPTest_q = expInf_uid24_fxpToFPTest_q; + default : expRPostExc_uid35_fxpToFPTest_q = 8'b0; + endcase + end + + // fracZ_uid27_fxpToFPTest(CONSTANT,26) + assign fracZ_uid27_fxpToFPTest_q = 23'b00000000000000000000000; + + // fracR_uid21_fxpToFPTest(BITSELECT,20)@6 + assign fracR_uid21_fxpToFPTest_in = expFracR_uid20_fxpToFPTest_q[23:0]; + assign fracR_uid21_fxpToFPTest_b = fracR_uid21_fxpToFPTest_in[23:1]; + + // redist7_fracR_uid21_fxpToFPTest_b_1(DELAY,98) + dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") ) + redist7_fracR_uid21_fxpToFPTest_b_1 ( .xin(fracR_uid21_fxpToFPTest_b), .xout(redist7_fracR_uid21_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) ); + + // excSelector_uid26_fxpToFPTest(LOGICAL,25)@7 + assign excSelector_uid26_fxpToFPTest_q = redist9_inIsZero_uid8_fxpToFPTest_q_2_q | ovf_uid25_fxpToFPTest_n | udf_uid23_fxpToFPTest_n; + + // fracRPostExc_uid28_fxpToFPTest(MUX,27)@7 + assign fracRPostExc_uid28_fxpToFPTest_s = excSelector_uid26_fxpToFPTest_q; + always @(fracRPostExc_uid28_fxpToFPTest_s or en or redist7_fracR_uid21_fxpToFPTest_b_1_q or fracZ_uid27_fxpToFPTest_q) + begin + unique case (fracRPostExc_uid28_fxpToFPTest_s) + 1'b0 : fracRPostExc_uid28_fxpToFPTest_q = redist7_fracR_uid21_fxpToFPTest_b_1_q; + 1'b1 : fracRPostExc_uid28_fxpToFPTest_q = fracZ_uid27_fxpToFPTest_q; + default : fracRPostExc_uid28_fxpToFPTest_q = 23'b0; + endcase + end + + // outRes_uid36_fxpToFPTest(BITJOIN,35)@7 + assign outRes_uid36_fxpToFPTest_q = {GND_q, expRPostExc_uid35_fxpToFPTest_q, fracRPostExc_uid28_fxpToFPTest_q}; + + // xOut(GPOUT,4)@7 + assign q = outRes_uid36_fxpToFPTest_q; + +endmodule diff --git a/hw/rtl/fp_cores/altera/dspba_library_ver.sv b/hw/rtl/fp_cores/altera/dspba_library_ver.sv new file mode 100644 index 00000000..16367ad0 --- /dev/null +++ b/hw/rtl/fp_cores/altera/dspba_library_ver.sv @@ -0,0 +1,392 @@ +// Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing device programming or simulation files), and +// any associated documentation or information are expressly subject to the +// terms and conditions of the Intel FPGA Software License Agreement, +// Intel MegaCore Function License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for the sole +// purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +module dspba_delay_ver +#( + parameter width = 8, + parameter depth = 1, + parameter reset_high = 1'b1, + parameter reset_kind = "ASYNC" +) ( + input clk, + input aclr, + input ena, + input [width-1:0] xin, + output [width-1:0] xout +); + + wire reset; + reg [width-1:0] delays [depth-1:0]; + + assign reset = aclr ^ reset_high; + + generate + if (depth > 0) + begin + genvar i; + for (i = 0; i < depth; ++i) + begin : delay_block + if (reset_kind == "ASYNC") + begin : sync_reset + always @ (posedge clk or negedge reset) + begin: a + if (!reset) begin + delays[i] <= 0; + end else begin + if (ena) begin + if (i > 0) begin + delays[i] <= delays[i - 1]; + end else begin + delays[i] <= xin; + end + end + end + end + end + + if (reset_kind == "SYNC") + begin : async_reset + always @ (posedge clk) + begin: a + if (!reset) begin + delays[i] <= 0; + end else begin + if (ena) begin + if (i > 0) begin + delays[i] <= delays[i - 1]; + end else begin + delays[i] <= xin; + end + end + end + end + end + + if (reset_kind == "NONE") + begin : no_reset + always @ (posedge clk) + begin: a + if (ena) begin + if (i > 0) begin + delays[i] <= delays[i - 1]; + end else begin + delays[i] <= xin; + end + end + end + end + end + + assign xout = delays[depth - 1]; + end else begin + assign xout = xin; + end + endgenerate + +endmodule + +//------------------------------------------------------------------------------ + +module dspba_sync_reg_ver +#( + parameter width1 = 8, + parameter width2 = 8, + parameter depth = 2, + parameter pulse_multiplier = 1, + parameter counter_width = 8, + parameter init_value = 0, + parameter reset1_high = 1'b1, + parameter reset2_high = 1'b1, + parameter reset_kind = "ASYNC" +) ( + input clk1, + input aclr1, + input [0 : 0] ena, + input [width1-1 : 0] xin, + output [width1-1 : 0] xout, + input clk2, + input aclr2, + output [width2-1 : 0] sxout +); +wire [width1-1 : 0] init_value_internal; + +wire reset1; +wire reset2; + +reg iclk_enable; +reg [width1-1 : 0] iclk_data; +reg [width2-1 : 0] oclk_data; + +// For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops +// For TimeQuest this means: identify these flip-flops as synchronizer to enable automatic MTBF analysis +(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-1 : 0] sync_regs; + +wire oclk_enable; + +wire ena_internal; +reg [counter_width-1 : 0] counter; + +assign init_value_internal = init_value; + +assign reset1 = aclr1 ^ reset1_high; +assign reset2 = aclr2 ^ reset2_high; + +generate + if (pulse_multiplier == 1) + begin: no_multiplication + assign ena_internal = ena[0]; + end +endgenerate + +generate + if (pulse_multiplier > 1) + begin: multiplu_ena_pulse + if (reset_kind == "ASYNC") + begin: async_reset + always @ (posedge clk1 or negedge reset1) + begin + if (reset1 == 1'b0) begin + counter <= 0; + end else begin + if (counter > 0) begin + if (counter == pulse_multiplier - 1) begin + counter <= 0; + end else begin + counter <= counter + 2'd1; + end + end else begin + if (ena[0] == 1'b1) begin + counter <= 1; + end + end + end + end + end + if (reset_kind == "SYNC") + begin: sync_reset + always @ (posedge clk1) + begin + if (reset1 == 1'b0) begin + counter <= 0; + end else begin + if (counter > 0) begin + if (counter == pulse_multiplier - 1) begin + counter <= 0; + end else begin + counter <= counter + 2'd1; + end + end else begin + if (ena[0] == 1'b1) begin + counter <= 1; + end + end + end + end + end + if (reset_kind == "NONE") + begin: no_reset + always @ (posedge clk1) + begin + if (counter > 0) begin + if (counter == pulse_multiplier - 1) begin + counter <= 0; + end else begin + counter <= counter + 2'd1; + end + end else begin + if (ena[0] == 1'b1) begin + counter <= 1; + end + end + end + end + + assign ena_internal = counter > 0 ? 1'b1 : ena[0]; + end +endgenerate + +assign oclk_enable = sync_regs[depth - 1]; + +generate + if (reset_kind == "ASYNC") + begin: iclk_async_reset + always @ (posedge clk1 or negedge reset1) + begin + if (reset1 == 1'b0) begin + iclk_data <= init_value_internal; + iclk_enable <= 1'b0; + end else begin + iclk_enable <= ena_internal; + if (ena[0] == 1'b1) begin + iclk_data <= xin; + end + end + end + end + if (reset_kind == "SYNC") + begin: iclk_sync_reset + always @ (posedge clk1) + begin + if (reset1 == 1'b0) begin + iclk_data <= init_value_internal; + iclk_enable <= 1'b0; + end else begin + iclk_enable <= ena_internal; + if (ena[0] == 1'b1) begin + iclk_data <= xin; + end + end + end + end + if (reset_kind == "NONE") + begin: iclk_no_reset + always @ (posedge clk1) + begin + iclk_enable <= ena_internal; + if (ena[0] == 1'b1) begin + iclk_data <= xin; + end + end + end +endgenerate + +generate + genvar i; + for (i = 0; i < depth; ++i) + begin: sync_regs_block + if (reset_kind == "ASYNC") + begin: sync_reg_async_reset + always @ (posedge clk2 or negedge reset2) begin + if (reset2 == 1'b0) begin + sync_regs[i] <= 1'b0; + end else begin + if (i > 0) begin + sync_regs[i] <= sync_regs[i - 1]; + end else begin + sync_regs[i] <= iclk_enable; + end + end + end + end + if (reset_kind == "SYNC") + begin: sync_reg_sync_reset + always @ (posedge clk2) begin + if (reset2 == 1'b0) begin + sync_regs[i] <= 1'b0; + end else begin + if (i > 0) begin + sync_regs[i] <= sync_regs[i - 1]; + end else begin + sync_regs[i] <= iclk_enable; + end + end + end + end + if (reset_kind == "NONE") + begin: sync_reg_no_reset + always @ (posedge clk2) begin + if (i > 0) begin + sync_regs[i] <= sync_regs[i - 1]; + end else begin + sync_regs[i] <= iclk_enable; + end + end + end + end +endgenerate + +generate + if (reset_kind == "ASYNC") + begin: oclk_async_reset + always @ (posedge clk2 or negedge reset2) + begin + if (reset2 == 1'b0) begin + oclk_data <= init_value_internal[width2-1 : 0]; + end else begin + if (oclk_enable == 1'b1) begin + oclk_data <= iclk_data[width2-1 : 0]; + end + end + end + end + if (reset_kind == "SYNC") + begin: oclk_sync_reset + always @ (posedge clk2) + begin + if (reset2 == 1'b0) begin + oclk_data <= init_value_internal[width2-1 : 0]; + end else begin + if (oclk_enable == 1'b1) begin + oclk_data <= iclk_data[width2-1 : 0]; + end + end + end + end + if (reset_kind == "NONE") + begin: oclk_no_reset + always @ (posedge clk2) + begin + if (oclk_enable == 1'b1) begin + oclk_data <= iclk_data[width2-1 : 0]; + end + end + end +endgenerate + +assign xout = iclk_data; +assign sxout = oclk_data; + +endmodule + +//------------------------------------------------------------------------------ + +module dspba_pipe +#( + parameter num_bits = 8, + parameter num_stages = 0, + parameter init_value = 1'bx +) ( + input clk, + input [num_bits-1:0] d, + output [num_bits-1:0] q +); + logic [num_bits-1:0] init_stage = { num_bits { init_value } }; + + generate + if (num_stages > 0) + begin + reg [num_bits-1:0] stage_array[num_stages-1:0]; + + genvar i; + for (i = 0; i < num_stages; ++i) + begin : g_pipe + always @ (posedge clk) begin + if (i>0) begin + stage_array[i] <= stage_array[i-1]; + end else begin + stage_array[i] <= d; + end + end + end + initial begin + stage_array = '{ num_stages { init_stage } }; + end + + assign q = stage_array[num_stages-1]; + + end else begin + assign q = d; + end + endgenerate + +endmodule diff --git a/hw/rtl/fp_cores/altera/generate.sh b/hw/rtl/fp_cores/altera/generate.sh new file mode 100755 index 00000000..550b56be --- /dev/null +++ b/hw/rtl/fp_cores/altera/generate.sh @@ -0,0 +1,25 @@ +#!/bin/bash + +CMD_POLY_EVAL_PATH=$QUARTUS_HOME/dspba/backend/linux64 + +OPTIONS="-target Arria10 -lang verilog -frequency 300 -enableHardFP 1 -printMachineReadable -faithfulRounding -noChanValid -enable -speedgrade 2" + +export LD_LIBRARY_PATH=$CMD_POLY_EVAL_PATH:$LD_LIBRARY_PATH + +CMD="$CMD_POLY_EVAL_PATH/cmdPolyEval $OPTIONS" + +EXP_BITS=8 +MAN_BITS=23 +FBITS="f$(($EXP_BITS + $MAN_BITS + 1))" + +echo Generating IP cores for $FBITS +{ + $CMD -name acl_fp_div FPDiv $EXP_BITS $MAN_BITS 0 + $CMD -name acl_fp_sqrt FPSqrt $EXP_BITS $MAN_BITS + $CMD -name acl_fp_ftoi FPToFXP $EXP_BITS $MAN_BITS 32 0 1 + $CMD -name acl_fp_ftou FPToFXP $EXP_BITS $MAN_BITS 32 0 0 + $CMD -name acl_fp_itof FXPToFP 32 0 1 $EXP_BITS $MAN_BITS + $CMD -name acl_fp_utof FXPToFP 32 0 0 $EXP_BITS $MAN_BITS +} > log.txt 2>&1 + +cp $QUARTUS_HOME/dspba/backend/Libraries/sv/base/dspba_library_ver.sv . \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_cmt_to_issue_if.v b/hw/rtl/interfaces/VX_cmt_to_issue_if.v index cff19de2..e083a3e5 100644 --- a/hw/rtl/interfaces/VX_cmt_to_issue_if.v +++ b/hw/rtl/interfaces/VX_cmt_to_issue_if.v @@ -20,12 +20,12 @@ interface VX_cmt_to_issue_if (); wire [`ISTAG_BITS-1:0] gpu_tag; `IGNORE_WARNINGS_BEGIN - is_data_t alu_data; - is_data_t lsu_data; - is_data_t csr_data; - is_data_t mul_data; - is_data_t fpu_data; - is_data_t gpu_data; + issue_data_t alu_data; + issue_data_t lsu_data; + issue_data_t csr_data; + issue_data_t mul_data; + issue_data_t fpu_data; + issue_data_t gpu_data; `IGNORE_WARNINGS_END endinterface diff --git a/hw/rtl/libs/VX_divide.v b/hw/rtl/libs/VX_divide.v index 3c871658..be13a186 100644 --- a/hw/rtl/libs/VX_divide.v +++ b/hw/rtl/libs/VX_divide.v @@ -31,7 +31,6 @@ module VX_divide #( .denom (denom), .quotient (quotient_unqual), .remain (remainder_unqual), - .aclr (1'b0), .clken (clk_en) ); @@ -41,7 +40,7 @@ module VX_divide #( divide.lpm_widthd = WIDTHD, divide.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED", divide.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED", - divide.lpm_hint = "MAXIMIZE_SPEED=9,LPM_REMAINDERPOSITIVE=FALSE", + divide.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE", divide.lpm_pipeline = PIPELINE; assign quotient = quotient_unqual [WIDTHQ-1:0]; diff --git a/hw/rtl/libs/VX_multiplier.v b/hw/rtl/libs/VX_multiplier.v index 3322b479..d5b7793c 100644 --- a/hw/rtl/libs/VX_multiplier.v +++ b/hw/rtl/libs/VX_multiplier.v @@ -23,8 +23,6 @@ module VX_multiplier #( .dataa (dataa), .datab (datab), .result (result), - .sclr (reset), - .aclr (1'b0), .clken (clk_en), .sum (1'b0) ); diff --git a/hw/rtl/libs/VX_shift_register.v b/hw/rtl/libs/VX_shift_register.v index c6a63ae1..b4f2496f 100644 --- a/hw/rtl/libs/VX_shift_register.v +++ b/hw/rtl/libs/VX_shift_register.v @@ -2,7 +2,7 @@ module VX_shift_register #( parameter DATAW = 1, - parameter DEPTH = 0 + parameter DEPTH = 1 ) ( input wire clk, input wire reset, @@ -10,41 +10,33 @@ module VX_shift_register #( input wire [DATAW-1:0] in, output wire [DATAW-1:0] out ); - if (0 == DEPTH) begin + reg [DEPTH-1:0][DATAW-1:0] entries; - assign out = in; - - end if (1 == DEPTH) begin - - reg [DATAW-1:0] ram; + if (1 == DEPTH) begin always @(posedge clk) begin if (reset) begin - ram <= '0; + entries <= '0; end else begin if (enable) begin - ram <= in; + entries <= in; end end end - assign out = ram; - - end else begin - - reg [DEPTH-1:0][DATAW-1:0] ram; + end else begin always @(posedge clk) begin if (reset) begin - ram <= '0; + entries <= '0; end else begin if (enable) begin - ram <= {ram[DEPTH-2:0], in}; + entries <= {entries[DEPTH-2:0], in}; end end end - - assign out = ram [DEPTH-1]; end + assign out = entries [DEPTH-1]; + endmodule \ No newline at end of file diff --git a/hw/syn/quartus/project.sdc b/hw/syn/quartus/project.sdc index 59686a41..61b8cba9 100644 --- a/hw/syn/quartus/project.sdc +++ b/hw/syn/quartus/project.sdc @@ -1,6 +1,6 @@ set_time_format -unit ns -decimal_places 3 -create_clock -name {clk} -period "200 MHz" -waveform { 0.0 1.0 } [get_ports {clk}] +create_clock -name {clk} -period "300 MHz" -waveform { 0.0 1.0 } [get_ports {clk}] derive_pll_clocks -create_base_clocks derive_clock_uncertainty