Interface Checkpoint 2 - Remove Lints

rtl/interfaces/VX_frE_to_bckE_req_inter.v

@@ -0,0 +1,90 @@
+
+`include "VX_define.v"
+
+`ifndef VX_FrE_to_BE_INTER
+
+`define VX_FrE_to_BE_INTER
+
+interface VX_frE_to_bckE_req_inter ();
+
+	wire[11:0]           csr_address;
+	wire                 is_csr;
+	wire[31:0]           csr_mask;
+	wire[4:0]            rd;
+	wire[4:0]            rs1;
+	wire[4:0]            rs2;
+	wire[`NT_M1:0][31:0] a_reg_data;
+	wire[`NT_M1:0][31:0] b_reg_data;
+	wire[4:0]            alu_op;
+	wire[1:0]            wb;
+	wire                 rs2_src;
+	wire[31:0]           itype_immed;
+	wire[2:0]            mem_read;
+	wire[2:0]            mem_write;
+	wire[2:0]            branch_type;
+	wire[19:0]           upper_immed;
+	wire[31:0]           curr_PC;
+	wire                 jal;
+	wire[31:0]           jal_offset;
+	wire[31:0]           PC_next;
+	wire[`NT_M1:0]       valid;
+	wire[`NW_M1:0]       warp_num;
+
+	// source-side view
+	modport snk (
+		input csr_address,
+		input is_csr,
+		input csr_mask,
+		input rd,
+		input rs1,
+		input rs2,
+		input a_reg_data,
+		input b_reg_data,
+		input alu_op,
+		input wb,
+		input rs2_src,
+		input itype_immed,
+		input mem_read,
+		input mem_write,
+		input branch_type,
+		input upper_immed,
+		input curr_PC,
+		input jal,
+		input jal_offset,
+		input PC_next,
+		input valid,
+		input warp_num
+	);
+
+
+	// source-side view
+	modport src (
+		output csr_address,
+		output is_csr,
+		output csr_mask,
+		output rd,
+		output rs1,
+		output rs2,
+		output a_reg_data,
+		output b_reg_data,
+		output alu_op,
+		output wb,
+		output rs2_src,
+		output itype_immed,
+		output mem_read,
+		output mem_write,
+		output branch_type,
+		output upper_immed,
+		output curr_PC,
+		output jal,
+		output jal_offset,
+		output PC_next,
+		output valid,
+		output warp_num
+	);
+
+
+endinterface
+
+
+`endif

rtl/interfaces/VX_inst_mem_wb_inter.v

@@ -0,0 +1,51 @@
+
+`include "VX_define.v"
+
+`ifndef VX_MEM_WB_INST_INTER
+
+`define VX_MEM_WB_INST_INTER
+
+interface VX_inst_mem_wb_inter ();
+
+		wire[`NT_M1:0][31:0] alu_result;
+		wire[`NT_M1:0][31:0] mem_result;
+		wire[4:0]            rd;
+		wire[1:0]            wb;
+		wire[4:0]            rs1;
+		wire[4:0]            rs2;
+		wire[31:0]           PC_next;
+		wire[`NT_M1:0]       valid;
+		wire[`NW_M1:0]       warp_num;
+
+	// source-side view
+	modport snk (
+		input alu_result,
+		input mem_result,
+		input rd,
+		input wb,
+		input rs1,
+		input rs2,
+		input PC_next,
+		input valid,
+		input warp_num
+	);
+
+
+	// source-side view
+	modport src (
+		output alu_result,
+		output mem_result,
+		output rd,
+		output wb,
+		output rs1,
+		output rs2,
+		output PC_next,
+		output valid,
+		output warp_num
+	);
+
+
+endinterface
+
+
+`endif

rtl/interfaces/VX_inst_meta_inter.v

@@ -0,0 +1,32 @@
+`include "VX_define.v"
+
+`ifndef VX_F_D_INTER
+
+`define VX_F_D_INTER
+
+interface VX_inst_meta_inter ();
+	wire[31:0]       instruction;
+	wire[31:0]       inst_pc;
+	wire[`NW_M1:0]   warp_num;
+	wire[`NT_M1:0]   valid;
+
+// source-side view
+modport snk (
+	input instruction,
+	input inst_pc,
+	input warp_num,
+	input valid
+);
+
+// sink-side view
+modport src (
+	output instruction,
+	output inst_pc,
+	output warp_num,
+	output valid
+);
+
+endinterface
+
+
+`endif

rtl/interfaces/VX_mem_req_inter.v

@@ -0,0 +1,55 @@
+interface VX_mem_req_inter ();
+
+	wire[`NT_M1:0][31:0] alu_result;
+	wire[2:0]            mem_read; 
+	wire[2:0]            mem_write;
+	wire[4:0]            rd;
+	wire[1:0]            wb;
+	wire[4:0]            rs1;
+	wire[4:0]            rs2;
+	wire[`NT_M1:0][31:0] rd2;
+	wire[31:0]           PC_next;
+	wire[31:0]           curr_PC;
+	wire[31:0]           branch_offset;
+	wire[2:0]            branch_type; 
+	wire[`NT_M1:0]       valid;
+	wire[`NW_M1:0]       warp_num;
+
+
+	modport snk (
+		input alu_result,
+		input mem_read, 
+		input mem_write,
+		input rd,
+		input wb,
+		input rs1,
+		input rs2,
+		input rd2,
+		input PC_next,
+		input curr_PC,
+		input branch_offset,
+		input branch_type, 
+		input valid,
+		input warp_num
+	);
+
+
+	modport src (
+		output alu_result,
+		output mem_read, 
+		output mem_write,
+		output rd,
+		output wb,
+		output rs1,
+		output rs2,
+		output rd2,
+		output PC_next,
+		output curr_PC,
+		output branch_offset,
+		output branch_type, 
+		output valid,
+		output warp_num
+	);
+
+
+endinterface

rtl/interfaces/VX_warp_ctl_inter.v

@@ -0,0 +1,42 @@
+
+`include "VX_define.v"
+
+`ifndef VX_WARP_CTL_INTER
+
+`define VX_WARP_CTL_INTER
+
+interface VX_warp_ctl_inter ();
+
+	wire[`NW_M1:0] warp_num;
+	wire           change_mask;
+	wire[`NT_M1:0] thread_mask;
+	wire           wspawn;
+	wire[31:0]     wspawn_pc;
+	wire           ebreak;
+
+	// source-side view
+	modport snk (
+		input warp_num,
+		input change_mask,
+		input thread_mask,
+		input wspawn,
+		input wspawn_pc,
+		input ebreak
+	);
+
+
+	// source-side view
+	modport src (
+		output warp_num,
+		output change_mask,
+		output thread_mask,
+		output wspawn,
+		output wspawn_pc,
+		output ebreak
+	);
+
+
+endinterface
+
+
+`endif

rtl/interfaces/VX_wb_inter.v

@@ -0,0 +1,38 @@
+
+`ifndef VX_WB_INTER
+
+`define VX_WB_INTER
+
+
+interface VX_wb_inter ();
+
+	wire[`NT_M1:0][31:0]     write_data; 
+	wire[4:0]      rd;
+	wire[1:0]      wb;
+	wire[`NT_M1:0]           wb_valid;
+	wire[`NW_M1:0] wb_warp_num;
+
+
+
+	modport snk (
+		input write_data,
+		input rd,
+		input wb,
+		input wb_valid,
+		input wb_warp_num
+	);
+
+
+	modport src (
+		output write_data,
+		output rd,
+		output wb,
+		output wb_valid,
+		output wb_warp_num
+	);
+
+endinterface
+
+
+
+`endif