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minor update

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This commit is contained in:
Blaise Tine
2021-07-15 14:39:41 -07:00
parent 0bec734532
commit f54d2b6272
3 changed files with 20 additions and 11 deletions
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11
hw/rtl/cache/VX_data_access.v vendored
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@@ -48,10 +48,17 @@ module VX_data_access #(
localparam BYTEENW = WRITE_ENABLE ? CACHE_LINE_SIZE : 1;
wire [`LINE_SELECT_BITS-1:0] line_addr;
wire [CACHE_LINE_SIZE-1:0] byte_enable;
wire [BYTEENW-1:0] byte_enable;
assign line_addr = addr[`LINE_SELECT_BITS-1:0];
assign byte_enable = is_fill ? {CACHE_LINE_SIZE{1'b1}} : byteen;
if (WRITE_ENABLE) begin
assign byte_enable = is_fill ? {BYTEENW{1'b1}} : byteen;
end else begin
`UNUSED_VAR (byteen)
`UNUSED_VAR (is_fill)
assign byte_enable = 1'b1;
end
VX_sp_ram #(
.DATAW (CACHE_LINE_SIZE * 8),