Define DBG_TRACE_CORE_PIPELINE_VCS for selective debug trace

2023-11-27 16:05:15 -08:00
parent 99207c862c
commit f41b50fc07
3 changed files with 3 additions and 3 deletions
--- a/hw/rtl/core/VX_dispatch.sv
+++ b/hw/rtl/core/VX_dispatch.sv
@@ -206,7 +206,7 @@ module VX_dispatch import VX_gpu_pkg::*; #(
    end
 `endif

-`ifdef DBG_TRACE_CORE_PIPELINE
+`ifdef DBG_TRACE_CORE_PIPELINE_VCS
    for (genvar i=0; i < `ISSUE_WIDTH; ++i) begin
        always @(posedge clk) begin
            if (operands_if[i].valid && operands_if[i].ready) begin