From f41b50fc07b03d1e6ee91cfecbe6750be61e44f5 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Mon, 27 Nov 2023 16:05:15 -0800 Subject: [PATCH] Define DBG_TRACE_CORE_PIPELINE_VCS for selective debug trace --- hw/rtl/core/VX_commit.sv | 2 +- hw/rtl/core/VX_decode.sv | 2 +- hw/rtl/core/VX_dispatch.sv | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/rtl/core/VX_commit.sv b/hw/rtl/core/VX_commit.sv index 8c760845..2a32d96c 100644 --- a/hw/rtl/core/VX_commit.sv +++ b/hw/rtl/core/VX_commit.sv @@ -195,7 +195,7 @@ module VX_commit import VX_gpu_pkg::*; #( end assign sim_wb_value = sim_wb_value_r; -`ifdef DBG_TRACE_CORE_PIPELINE +`ifdef DBG_TRACE_CORE_PIPELINE_VCS for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin always @(posedge clk) begin if (alu_commit_if[i].valid && alu_commit_if[i].ready) begin diff --git a/hw/rtl/core/VX_decode.sv b/hw/rtl/core/VX_decode.sv index 0032fe7b..459b9762 100644 --- a/hw/rtl/core/VX_decode.sv +++ b/hw/rtl/core/VX_decode.sv @@ -536,7 +536,7 @@ module VX_decode #( assign fetch_if.ibuf_pop = decode_if.ibuf_pop; -`ifdef DBG_TRACE_CORE_PIPELINE +`ifdef DBG_TRACE_CORE_PIPELINE_VCS always @(posedge clk) begin if (decode_if.valid && decode_if.ready) begin `TRACE(1, ("%d: core%0d-decode: wid=%0d, PC=0x%0h, instr=0x%0h, ex=", $time, CORE_ID, decode_if.data.wid, decode_if.data.PC, instr)); diff --git a/hw/rtl/core/VX_dispatch.sv b/hw/rtl/core/VX_dispatch.sv index efd719be..f10caa47 100644 --- a/hw/rtl/core/VX_dispatch.sv +++ b/hw/rtl/core/VX_dispatch.sv @@ -206,7 +206,7 @@ module VX_dispatch import VX_gpu_pkg::*; #( end `endif -`ifdef DBG_TRACE_CORE_PIPELINE +`ifdef DBG_TRACE_CORE_PIPELINE_VCS for (genvar i=0; i < `ISSUE_WIDTH; ++i) begin always @(posedge clk) begin if (operands_if[i].valid && operands_if[i].ready) begin