wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis

Browse Source
This commit is contained in:
Blaise Tine
2020-04-05 18:09:43 -04:00
parent adf8e7dcd5 7e8a1a6698
commit e9052259fb
18 changed files with 36 additions and 86075 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
benchmarks/new_opencl/bfs/Makefile
View File

@@ -7,7 +7,7 @@ CXXFLAGS += -std=c++11 -O0 -g -fpermissive -Wall -Wextra -pedantic -Wfatal-error
CXXFLAGS += -I$(POCLRT_PATH)/include
LDFLAGS += -L$(POCLRT_PATH)/lib -L$(DRIVER_PATH)/simx -lOpenCL -lvortex
LDFLAGS += -L$(POCLRT_PATH)/lib -L$(DRIVER_PATH)/dummy -lOpenCL -lvortex
PROJECT = bfs
@@ -25,7 +25,7 @@ run-fpga: $(PROJECT) kernel.pocl
LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT)
run-ase: $(PROJECT) kernel.pocl
LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT)
ASE_LOG=0 LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT)
run-simx: $(PROJECT) kernel.pocl
LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT)

4
benchmarks/new_opencl/guassian/Makefile
View File

@@ -7,7 +7,7 @@ CXXFLAGS += -std=c++11 -O0 -g -fpermissive -Wall -Wextra -pedantic -Wfatal-error
CXXFLAGS += -I$(POCLRT_PATH)/include
LDFLAGS += -L$(POCLRT_PATH)/lib -L$(DRIVER_PATH)/simx -lOpenCL -lvortex
LDFLAGS += -L$(POCLRT_PATH)/lib -L$(DRIVER_PATH)/dummy -lOpenCL -lvortex
PROJECT = guassian
@@ -25,7 +25,7 @@ run-fpga: $(PROJECT) kernel.pocl
LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT)
run-ase: $(PROJECT) kernel.pocl
LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT)
ASE_LOG=0 LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT)
run-simx: $(PROJECT) kernel.pocl
LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT)

4
benchmarks/new_opencl/kmeans/Makefile
View File

@@ -7,7 +7,7 @@ CXXFLAGS += -std=c++11 -O0 -g -fpermissive -Wall -Wextra -pedantic -Wfatal-error
CXXFLAGS += -I$(POCLRT_PATH)/include
LDFLAGS += -L$(POCLRT_PATH)/lib -L$(DRIVER_PATH)/simx -lOpenCL -lvortex
LDFLAGS += -L$(POCLRT_PATH)/lib -L$(DRIVER_PATH)/dummy -lOpenCL -lvortex
PROJECT = kmeans
@@ -25,7 +25,7 @@ run-fpga: $(PROJECT) kernel.pocl
LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT)
run-ase: $(PROJECT) kernel.pocl
LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT)
ASE_LOG=0 LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT)
run-simx: $(PROJECT) kernel.pocl
LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT)

4
benchmarks/new_opencl/nearn/Makefile
View File

@@ -7,7 +7,7 @@ CXXFLAGS += -std=c++11 -O0 -g -fpermissive -Wall -Wextra -pedantic -Wfatal-error
CXXFLAGS += -I$(POCLRT_PATH)/include
LDFLAGS += -L$(POCLRT_PATH)/lib -L$(DRIVER_PATH)/simx -lOpenCL -lvortex
LDFLAGS += -L$(POCLRT_PATH)/lib -L$(DRIVER_PATH)/dummy -lOpenCL -lvortex
PROJECT = nearn
@@ -25,7 +25,7 @@ run-fpga: $(PROJECT) kernel.pocl
LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT)
run-ase: $(PROJECT) kernel.pocl
LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT)
ASE_LOG=0 LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT)
run-simx: $(PROJECT) kernel.pocl
LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT)

4
benchmarks/new_opencl/saxpy/Makefile
View File

@@ -7,7 +7,7 @@ CXXFLAGS += -std=c++11 -O0 -g -fpermissive -Wall -Wextra -pedantic -Wfatal-error
CXXFLAGS += -I$(POCLRT_PATH)/include
LDFLAGS += -L$(POCLRT_PATH)/lib -L$(DRIVER_PATH)/simx -lOpenCL -lvortex
LDFLAGS += -L$(POCLRT_PATH)/lib -L$(DRIVER_PATH)/dummy -lOpenCL -lvortex
PROJECT = saxpy
@@ -25,7 +25,7 @@ run-fpga: $(PROJECT) kernel.pocl
LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT)
run-ase: $(PROJECT) kernel.pocl
LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT)
ASE_LOG=0 LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT)
run-simx: $(PROJECT) kernel.pocl
LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT)

4
benchmarks/new_opencl/sfilter/Makefile
View File

@@ -7,7 +7,7 @@ CXXFLAGS += -std=c++11 -O0 -g -fpermissive -Wall -Wextra -pedantic -Wfatal-error
CXXFLAGS += -I$(POCLRT_PATH)/include
LDFLAGS += -L$(POCLRT_PATH)/lib -L$(DRIVER_PATH)/simx -lOpenCL -lvortex
LDFLAGS += -L$(POCLRT_PATH)/lib -L$(DRIVER_PATH)/dummy -lOpenCL -lvortex
PROJECT = sfilter
@@ -25,7 +25,7 @@ run-fpga: $(PROJECT) kernel.pocl
LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT)
run-ase: $(PROJECT) kernel.pocl
LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT)
ASE_LOG=0 LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT)
run-simx: $(PROJECT) kernel.pocl
LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT)

4
benchmarks/new_opencl/sgemm/Makefile
View File

@@ -7,7 +7,7 @@ CXXFLAGS += -std=c++11 -O0 -g -fpermissive -Wall -Wextra -pedantic -Wfatal-error
CXXFLAGS += -I$(POCLRT_PATH)/include
LDFLAGS += -L$(POCLRT_PATH)/lib -L$(DRIVER_PATH)/simx -lOpenCL -lvortex
LDFLAGS += -L$(POCLRT_PATH)/lib -L$(DRIVER_PATH)/dummy -lOpenCL -lvortex
PROJECT = sgemm
@@ -25,7 +25,7 @@ run-fpga: $(PROJECT) kernel.pocl
LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT)
run-ase: $(PROJECT) kernel.pocl
LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT)
ASE_LOG=0 LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT)
run-simx: $(PROJECT) kernel.pocl
LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT)

4
benchmarks/new_opencl/vecadd/Makefile
View File

@@ -7,7 +7,7 @@ CXXFLAGS += -std=c++11 -O0 -g -fpermissive -Wall -Wextra -pedantic -Wfatal-error
CXXFLAGS += -I$(POCLRT_PATH)/include
LDFLAGS += -L$(POCLRT_PATH)/lib -L$(DRIVER_PATH)/simx -lOpenCL -lvortex
LDFLAGS += -L$(POCLRT_PATH)/lib -L$(DRIVER_PATH)/dummy -lOpenCL -lvortex
PROJECT = vecadd
@@ -25,7 +25,7 @@ run-fpga: $(PROJECT) kernel.pocl
LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT)
run-ase: $(PROJECT) kernel.pocl
LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT)
ASE_LOG=0 LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT)
run-simx: $(PROJECT) kernel.pocl
LD_LIBRARY_PATH=$(POCLRT_PATH)/lib:$(DRIVER_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT)

17
driver/hw/vortex_afu.sv
View File

@@ -194,7 +194,6 @@ logic [31:0] avs_read_ctr;
logic [31:0] avs_write_ctr;
logic [31:0] vx_snoop_ctr;
logic [9:0] vx_snoop_delay;
logic [1:0] vx_snoop_level;
logic vx_reset;
always_ff @(posedge clk)
@@ -248,13 +247,12 @@ begin
STATE_RUN: begin
if (vx_ebreak)
begin
// TODO: Add delay stage before returning to IDLE
state <= STATE_IDLE;
end
end
STATE_CLFLUSH: begin
if (vx_snoop_level >= VX_SNOOP_LEVELS)
if (vx_snoop_delay >= VX_SNOOP_DELAY)
begin
state <= STATE_IDLE;
end
@@ -521,21 +519,18 @@ begin
vx_snp_req <= 0;
vx_snoop_ctr <= 0;
vx_snoop_delay <= 0;
vx_snoop_level <= 0;
end
else begin
if (STATE_IDLE == state)
begin
vx_snoop_ctr <= 0;
vx_snoop_delay <= 0;
vx_snoop_level <= 0;
end
vx_snp_req <= 0;
if ((STATE_CLFLUSH == state)
&& vx_snoop_ctr < csr_data_size
&& vx_snoop_level < VX_SNOOP_LEVELS
&& !vx_snp_req_delay)
begin
vx_snp_req_addr <= (csr_mem_addr + vx_snoop_ctr) << 6;
@@ -543,18 +538,10 @@ begin
vx_snoop_ctr <= vx_snoop_ctr + 1;
end
if ((vx_snoop_ctr == csr_data_size)
&& (vx_snoop_delay < VX_SNOOP_DELAY))
if (vx_snoop_ctr == csr_data_size)
begin
vx_snoop_delay <= vx_snoop_delay + 1;
end
if (vx_snoop_delay == VX_SNOOP_DELAY)
begin
vx_snoop_ctr <= 0;
vx_snoop_delay <= 0;
vx_snoop_level <= vx_snoop_level + 1;
end
end
end

4
driver/hw/wave.do
View File

@@ -50,7 +50,7 @@ add wave -noupdate -label warp_stalled {/ase_top/ase_top_generic/platform_shim_c
add wave -noupdate -label warp_lock {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/warp_scheduler/warp_lock}
add wave -noupdate -label use_active {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/warp_scheduler/use_active}
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 2} {293228800 ps} 0}
WaveRestoreCursors {{Cursor 2} {360293 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 195
configure wave -valuecolwidth 100
@@ -66,4 +66,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {293046456 ps} {293411144 ps}
WaveRestoreZoom {346453 ps} {711141 ps}

2
driver/sw/opae/Makefile
View File

@@ -65,4 +65,4 @@ clean:
ifneq ($(MAKECMDGOALS),clean)
-include .depend
endif
endif

BIN
driver/tests/basic/basic
View File

Binary file not shown.

2
driver/tests/demo/Makefile
View File

@@ -46,7 +46,7 @@ run-fpga: $(PROJECT)
LD_LIBRARY_PATH=../../sw/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) -f kernel.bin -n 16
run-ase: $(PROJECT)
ASE_LOG=0 LD_LIBRARY_PATH=../../sw/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) -f kernel.bin -n 1
ASE_LOG=0 LD_LIBRARY_PATH=../../sw/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) -f kernel.bin -n 16
run-rtlsim: $(PROJECT)
LD_LIBRARY_PATH=../../sw/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) -f kernel.bin -n 16

BIN
driver/tests/demo/demo
View File

Binary file not shown.

86035
driver/tests/demo/kernel.dump
View File

File diff suppressed because it is too large Load Diff

4
rtl/VX_alu.v
View File

@@ -135,7 +135,7 @@ module VX_alu(
assign upper_immed = {in_upper_immed, {12{1'b0}}};
always @(in_alu_op or ALU_in1 or ALU_in2) begin
always @(*) begin
case(in_alu_op)
`ADD: out_alu_result = $signed(ALU_in1) + $signed(ALU_in2);
`SUB: out_alu_result = $signed(ALU_in1) - $signed(ALU_in2);
@@ -177,7 +177,7 @@ module VX_alu(
assign upper_immed = {in_upper_immed, {12{1'b0}}};
always @(in_alu_op or ALU_in1 or ALU_in2) begin
always @(*) begin
case(in_alu_op)
`ADD: out_alu_result = $signed(ALU_in1) + $signed(ALU_in2);
`SUB: out_alu_result = $signed(ALU_in1) - $signed(ALU_in2);

4
rtl/VX_cache/VX_tag_data_structure.v
View File

@@ -88,9 +88,9 @@ module VX_tag_data_structure
if (reset) begin
for (l = 0; l < `BANK_LINE_COUNT; l=l+1) begin
valid[l] <= 0;
tag [l] <= 0;
// tag [l] <= 0;
dirty[l] <= 0;
data [l] <= 0;
// data [l] <= 0;
end
end else if (!stall_bank_pipe) begin
if (going_to_write) begin

11
rtl/VX_front_end.v
View File

@@ -40,7 +40,16 @@ wire terminate_sim;
wire[`NW_M1:0] icache_stage_wid;
wire[`NT-1:0] icache_stage_valids;
assign fetch_ebreak = vortex_ebreak || terminate_sim;
reg old_ebreak; // This should be eventually removed
always @(posedge clk) begin
if (reset) begin
old_ebreak <= 0;
end else begin
old_ebreak <= old_ebreak || fetch_ebreak;
end
end
assign fetch_ebreak = vortex_ebreak || terminate_sim || old_ebreak;
VX_wstall_inter VX_wstall();