RTL code refactoring
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@@ -41,7 +41,7 @@ module Vortex #(
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// LLC Snooping
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input wire llc_snp_req_valid,
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input wire [31:0] llc_snp_req_addr,
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output wire llc_snp_req_full,
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output wire llc_snp_req_ready,
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output wire out_ebreak
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);
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@@ -122,7 +122,7 @@ module Vortex #(
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generate
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for (j = 0; j < `IBANK_LINE_WORDS; j = j + 1) begin
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assign gpu_icache_dram_res_if.dram_rsp_data[j] = I_dram_rsp_data[j * 32 +: 32];
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assign I_dram_req_data[j * 32 +: 32] = gpu_icache_dram_req_if.dram_req_data[j];
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assign I_dram_req_data[j * 32 +: 32] = gpu_icache_dram_req_if.dram_req_data[j];
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end
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endgenerate
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@@ -144,7 +144,7 @@ VX_gpu_snp_req_rsp_if gpu_icache_snp_req_if();
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VX_gpu_snp_req_rsp_if gpu_dcache_snp_req_if();
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assign gpu_dcache_snp_req_if.snp_req_valid = llc_snp_req_valid;
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assign gpu_dcache_snp_req_if.snp_req_addr = llc_snp_req_addr;
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assign llc_snp_req_full = gpu_dcache_snp_req_if.snp_req_full;
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assign llc_snp_req_ready = gpu_dcache_snp_req_if.snp_req_ready;
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VX_front_end front_end (
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.clk (clk),
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