From e8072bab770b42e81afe63d0cd9c111861f5c824 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Mon, 20 Apr 2020 11:20:41 -0400 Subject: [PATCH] RTL code refactoring --- hw/rtl/VX_dmem_controller.v | 12 +++---- hw/rtl/Vortex.v | 6 ++-- hw/rtl/Vortex_Cluster.v | 12 +++---- hw/rtl/Vortex_Socket.v | 14 ++++---- hw/rtl/generic_cache/VX_cache.v | 40 +++++++++++------------ hw/rtl/generic_cache/VX_snp_fwd_arb.v | 27 +++++++-------- hw/rtl/interfaces/VX_gpu_snp_req_rsp_if.v | 2 +- hw/simulate/simulator.cpp | 2 +- 8 files changed, 56 insertions(+), 59 deletions(-) diff --git a/hw/rtl/VX_dmem_controller.v b/hw/rtl/VX_dmem_controller.v index 55c049de..83db3804 100644 --- a/hw/rtl/VX_dmem_controller.v +++ b/hw/rtl/VX_dmem_controller.v @@ -143,7 +143,7 @@ module VX_dmem_controller ( .snp_req_valid (0), .snp_req_addr (0), `IGNORE_WARNINGS_BEGIN - .snp_req_full (), + .snp_req_ready (), `IGNORE_WARNINGS_END // Snoop Forward @@ -151,7 +151,7 @@ module VX_dmem_controller ( .snp_fwd_valid (), .snp_fwd_addr (), `IGNORE_WARNINGS_END - .snp_fwd_full (0) + .snp_fwd_ready (0) ); VX_cache #( @@ -225,14 +225,14 @@ module VX_dmem_controller ( // Snoop Request .snp_req_valid (gpu_dcache_snp_req_if.snp_req_valid), .snp_req_addr (gpu_dcache_snp_req_if.snp_req_addr), - .snp_req_full (gpu_dcache_snp_req_if.snp_req_full), + .snp_req_ready (gpu_dcache_snp_req_if.snp_req_ready), // Snoop Forward `IGNORE_WARNINGS_BEGIN .snp_fwd_valid (), .snp_fwd_addr (), `IGNORE_WARNINGS_END - .snp_fwd_full (0) + .snp_fwd_ready (0) ); VX_cache #( @@ -306,14 +306,14 @@ module VX_dmem_controller ( // Snoop Request .snp_req_valid (gpu_icache_snp_req_if.snp_req_valid), .snp_req_addr (gpu_icache_snp_req_if.snp_req_addr), - .snp_req_full (gpu_icache_snp_req_if.snp_req_full), + .snp_req_ready (gpu_icache_snp_req_if.snp_req_ready), // Snoop Forward `IGNORE_WARNINGS_BEGIN .snp_fwd_valid (), .snp_fwd_addr (), `IGNORE_WARNINGS_END - .snp_fwd_full (0) + .snp_fwd_ready (0) ); endmodule diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index cbbec006..f891a287 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -41,7 +41,7 @@ module Vortex #( // LLC Snooping input wire llc_snp_req_valid, input wire [31:0] llc_snp_req_addr, - output wire llc_snp_req_full, + output wire llc_snp_req_ready, output wire out_ebreak ); @@ -122,7 +122,7 @@ module Vortex #( generate for (j = 0; j < `IBANK_LINE_WORDS; j = j + 1) begin assign gpu_icache_dram_res_if.dram_rsp_data[j] = I_dram_rsp_data[j * 32 +: 32]; - assign I_dram_req_data[j * 32 +: 32] = gpu_icache_dram_req_if.dram_req_data[j]; + assign I_dram_req_data[j * 32 +: 32] = gpu_icache_dram_req_if.dram_req_data[j]; end endgenerate @@ -144,7 +144,7 @@ VX_gpu_snp_req_rsp_if gpu_icache_snp_req_if(); VX_gpu_snp_req_rsp_if gpu_dcache_snp_req_if(); assign gpu_dcache_snp_req_if.snp_req_valid = llc_snp_req_valid; assign gpu_dcache_snp_req_if.snp_req_addr = llc_snp_req_addr; -assign llc_snp_req_full = gpu_dcache_snp_req_if.snp_req_full; +assign llc_snp_req_ready = gpu_dcache_snp_req_if.snp_req_ready; VX_front_end front_end ( .clk (clk), diff --git a/hw/rtl/Vortex_Cluster.v b/hw/rtl/Vortex_Cluster.v index 0470d4f5..9102f0a6 100644 --- a/hw/rtl/Vortex_Cluster.v +++ b/hw/rtl/Vortex_Cluster.v @@ -28,7 +28,7 @@ module Vortex_Cluster #( // LLC Snooping input wire llc_snp_req_valid, input wire[31:0] llc_snp_req_addr, - output wire llc_snp_req_full, + output wire llc_snp_req_ready, output wire out_ebreak ); @@ -66,7 +66,7 @@ module Vortex_Cluster #( wire snp_fwd_valid; wire[31:0] snp_fwd_addr; - wire[`NUM_CORES_PER_CLUSTER-1:0] snp_fwd_full; + wire[`NUM_CORES_PER_CLUSTER-1:0] snp_fwd_ready; assign out_ebreak = (&per_core_out_ebreak); @@ -83,7 +83,7 @@ module Vortex_Cluster #( Vortex #( .CORE_ID(curr_core + (CLUSTER_ID * `NUM_CORES_PER_CLUSTER)) - ) vortex_core( + ) vortex_core ( .clk (clk), .reset (reset), .io_valid (per_core_io_valid [curr_core]), @@ -108,7 +108,7 @@ module Vortex_Cluster #( .I_dram_rsp_ready (per_core_I_dram_rsp_ready [curr_core]), .llc_snp_req_valid (snp_fwd_valid), .llc_snp_req_addr (snp_fwd_addr), - .llc_snp_req_full (snp_fwd_full [curr_core]), + .llc_snp_req_ready (snp_fwd_ready [curr_core]), .out_ebreak (per_core_out_ebreak [curr_core]) ); @@ -252,11 +252,11 @@ module Vortex_Cluster #( // Snoop Request .snp_req_valid (llc_snp_req_valid), .snp_req_addr (llc_snp_req_addr), - .snp_req_full (llc_snp_req_full), + .snp_req_ready (llc_snp_req_ready), .snp_fwd_valid (snp_fwd_valid), .snp_fwd_addr (snp_fwd_addr), - .snp_fwd_full (|snp_fwd_full) + .snp_fwd_ready (& snp_fwd_ready) ); endmodule \ No newline at end of file diff --git a/hw/rtl/Vortex_Socket.v b/hw/rtl/Vortex_Socket.v index bb0f230e..9ae17953 100644 --- a/hw/rtl/Vortex_Socket.v +++ b/hw/rtl/Vortex_Socket.v @@ -26,7 +26,7 @@ module Vortex_Socket ( // LLC Snooping input wire llc_snp_req_valid, input wire[31:0] llc_snp_req_addr, - output wire llc_snp_req_full, + output wire llc_snp_req_ready, output wire out_ebreak ); @@ -61,7 +61,7 @@ module Vortex_Socket ( .llc_snp_req_valid (llc_snp_req_valid), .llc_snp_req_addr (llc_snp_req_addr), - .llc_snp_req_full (llc_snp_req_full), + .llc_snp_req_ready (llc_snp_req_ready), .out_ebreak (out_ebreak) ); @@ -70,7 +70,7 @@ module Vortex_Socket ( wire snp_fwd_valid; wire[31:0] snp_fwd_addr; - wire[`NUM_CLUSTERS-1:0] snp_fwd_full; + wire[`NUM_CLUSTERS-1:0] snp_fwd_ready; wire[`NUM_CLUSTERS-1:0] per_cluster_out_ebreak; @@ -114,7 +114,7 @@ module Vortex_Socket ( Vortex_Cluster #( .CLUSTER_ID(curr_cluster) - ) Vortex_Cluster( + ) Vortex_Cluster ( .clk (clk), .reset (reset), .io_valid (per_cluster_io_valid [curr_cluster]), @@ -133,7 +133,7 @@ module Vortex_Socket ( .llc_snp_req_valid (snp_fwd_valid), .llc_snp_req_addr (snp_fwd_addr), - .llc_snp_req_full (snp_fwd_full[curr_cluster]), + .llc_snp_req_ready (snp_fwd_ready[curr_cluster]), .out_ebreak (per_cluster_out_ebreak [curr_cluster]) ); @@ -253,12 +253,12 @@ module Vortex_Socket ( // Snoop Request .snp_req_valid (llc_snp_req_valid), .snp_req_addr (llc_snp_req_addr), - .snp_req_full (llc_snp_req_full), + .snp_req_ready (llc_snp_req_ready), // Snoop Forward .snp_fwd_valid (snp_fwd_valid), .snp_fwd_addr (snp_fwd_addr), - .snp_fwd_full (|snp_fwd_full) + .snp_fwd_ready (& snp_fwd_ready) ); end diff --git a/hw/rtl/generic_cache/VX_cache.v b/hw/rtl/generic_cache/VX_cache.v index 904e7271..11596000 100644 --- a/hw/rtl/generic_cache/VX_cache.v +++ b/hw/rtl/generic_cache/VX_cache.v @@ -94,12 +94,12 @@ module VX_cache #( // Snoop Req input wire snp_req_valid, input wire [31:0] snp_req_addr, - output wire snp_req_full, + output wire snp_req_ready, // Snoop Forward output wire snp_fwd_valid, output wire [31:0] snp_fwd_addr, - input wire snp_fwd_full + input wire snp_fwd_ready ); wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valids; @@ -128,14 +128,14 @@ module VX_cache #( wire [NUM_BANKS-1:0][`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] per_bank_dram_wb_req_data; wire [NUM_BANKS-1:0] per_bank_reqq_full; - wire [NUM_BANKS-1:0] per_bank_snrq_full; + wire [NUM_BANKS-1:0] per_bank_snp_req_full; - wire [NUM_BANKS-1:0] per_bank_snp_fwd; + wire [NUM_BANKS-1:0] per_bank_snp_fwd_valid; wire [NUM_BANKS-1:0][31:0] per_bank_snp_fwd_addr; wire [NUM_BANKS-1:0] per_bank_snp_fwd_pop; assign core_req_ready = ~(|per_bank_reqq_full); - assign snp_req_full = (|per_bank_snrq_full); + assign snp_req_ready = ~(|per_bank_snp_req_full); // assign dram_rsp_ready = (NUM_BANKS == 1) ? per_bank_dram_fill_rsp_ready[0] : per_bank_dram_fill_rsp_ready[dram_rsp_addr[`BANK_SELECT_ADDR_RNG]]; assign dram_rsp_ready = (|per_bank_dram_fill_rsp_ready); @@ -242,12 +242,12 @@ module VX_cache #( VX_snp_fwd_arb #( .NUM_BANKS(NUM_BANKS) ) snp_fwd_arb( - .per_bank_snp_fwd (per_bank_snp_fwd), - .per_bank_snp_fwd_addr(per_bank_snp_fwd_addr), - .per_bank_snp_fwd_pop (per_bank_snp_fwd_pop), - .snp_fwd_valid (snp_fwd_valid), - .snp_fwd_addr (snp_fwd_addr), - .snp_fwd_full (snp_fwd_full) + .per_bank_snp_fwd_valid (per_bank_snp_fwd_valid), + .per_bank_snp_fwd_addr (per_bank_snp_fwd_addr), + .per_bank_snp_fwd_pop (per_bank_snp_fwd_pop), + .snp_fwd_valid (snp_fwd_valid), + .snp_fwd_addr (snp_fwd_addr), + .snp_fwd_ready (snp_fwd_ready) ); // Snoop Forward Logic @@ -295,7 +295,7 @@ module VX_cache #( wire curr_bank_reqq_full; - wire curr_bank_snp_fwd; + wire curr_bank_snp_fwd_valid; wire[31:0] curr_bank_snp_fwd_addr; wire curr_bank_snp_fwd_pop; wire curr_bank_snp_req_full; @@ -342,14 +342,14 @@ module VX_cache #( assign per_bank_dram_wb_req_data[curr_bank] = curr_bank_dram_wb_req_data; // Snoop Request - assign curr_bank_snp_req = snp_req_valid && (snp_req_addr[`BANK_SELECT_ADDR_RNG] == curr_bank); - assign curr_bank_snp_req_addr = snp_req_addr; - assign per_bank_snrq_full[curr_bank] = curr_bank_snp_req_full; + assign curr_bank_snp_req = snp_req_valid && (snp_req_addr[`BANK_SELECT_ADDR_RNG] == curr_bank); + assign curr_bank_snp_req_addr = snp_req_addr; + assign per_bank_snp_req_full[curr_bank] = curr_bank_snp_req_full; - // Snoop Fwd - assign curr_bank_snp_fwd_pop = per_bank_snp_fwd_pop[curr_bank]; - assign per_bank_snp_fwd[curr_bank] = curr_bank_snp_fwd; - assign per_bank_snp_fwd_addr[curr_bank] = curr_bank_snp_fwd_addr; + // Snoop Fwd + assign per_bank_snp_fwd_valid[curr_bank] = curr_bank_snp_fwd_valid; + assign per_bank_snp_fwd_addr[curr_bank] = curr_bank_snp_fwd_addr; + assign curr_bank_snp_fwd_pop = per_bank_snp_fwd_pop[curr_bank]; VX_bank #( .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES), @@ -421,7 +421,7 @@ module VX_cache #( .snp_req_full (curr_bank_snp_req_full), // Snoop forwarding - .snp_fwd_valid (curr_bank_snp_fwd), + .snp_fwd_valid (curr_bank_snp_fwd_valid), .snp_fwd_addr (curr_bank_snp_fwd_addr), .snp_fwd_pop (curr_bank_snp_fwd_pop) ); diff --git a/hw/rtl/generic_cache/VX_snp_fwd_arb.v b/hw/rtl/generic_cache/VX_snp_fwd_arb.v index d22b6cd5..f37f0970 100644 --- a/hw/rtl/generic_cache/VX_snp_fwd_arb.v +++ b/hw/rtl/generic_cache/VX_snp_fwd_arb.v @@ -1,31 +1,28 @@ `include "VX_cache_config.vh" -module VX_snp_fwd_arb - #( - parameter NUM_BANKS = 8 - ) - ( - input wire [NUM_BANKS-1:0] per_bank_snp_fwd, +module VX_snp_fwd_arb #( + parameter NUM_BANKS = 8 +) ( + input wire [NUM_BANKS-1:0] per_bank_snp_fwd_valid, input wire [NUM_BANKS-1:0][31:0] per_bank_snp_fwd_addr, - output reg [NUM_BANKS-1:0] per_bank_snp_fwd_pop, + output reg [NUM_BANKS-1:0] per_bank_snp_fwd_pop, output wire snp_fwd_valid, output wire [31:0] snp_fwd_addr, - input wire snp_fwd_full - + input wire snp_fwd_ready ); - wire[NUM_BANKS-1:0] qual_per_bank_snp_fwd = per_bank_snp_fwd & {NUM_BANKS{!snp_fwd_full}}; + wire [NUM_BANKS-1:0] qual_per_bank_snp_fwd = per_bank_snp_fwd_valid & {NUM_BANKS{snp_fwd_ready}}; - wire[`LOG2UP(NUM_BANKS)-1:0] fsq_bank; - wire fsq_valid; + wire [`LOG2UP(NUM_BANKS)-1:0] fsq_bank; + wire fsq_valid; VX_generic_priority_encoder #( .N(NUM_BANKS) ) sel_ffsq ( - .valids(qual_per_bank_snp_fwd), - .index (fsq_bank), - .found (fsq_valid) + .valids (qual_per_bank_snp_fwd), + .index (fsq_bank), + .found (fsq_valid) ); assign snp_fwd_valid = fsq_valid; diff --git a/hw/rtl/interfaces/VX_gpu_snp_req_rsp_if.v b/hw/rtl/interfaces/VX_gpu_snp_req_rsp_if.v index ce6c1923..e205b6e4 100644 --- a/hw/rtl/interfaces/VX_gpu_snp_req_rsp_if.v +++ b/hw/rtl/interfaces/VX_gpu_snp_req_rsp_if.v @@ -8,7 +8,7 @@ interface VX_gpu_snp_req_rsp_if (); // Snoop request wire snp_req_valid; wire [31:0] snp_req_addr; - wire snp_req_full; + wire snp_req_ready; // Snoop Response // TODO: diff --git a/hw/simulate/simulator.cpp b/hw/simulate/simulator.cpp index 3645cfad..a2521154 100644 --- a/hw/simulate/simulator.cpp +++ b/hw/simulate/simulator.cpp @@ -277,7 +277,7 @@ void Simulator::send_snoops(uint32_t mem_addr, uint32_t size) { break; vortex_->llc_snp_req_addr += GLOBAL_BLOCK_SIZE_BYTES; } - if (!vortex_->llc_snp_req_full) { + if (vortex_->llc_snp_req_ready) { vortex_->llc_snp_req_valid = true; } }