Fix issues quartus synthesis issues

2020-02-18 13:24:18 -05:00
parent d71f8fcc73
commit e76d05f7ce
6 changed files with 15 additions and 10 deletions
--- a/rtl/VX_csr_data.v
+++ b/rtl/VX_csr_data.v
@@ -57,7 +57,7 @@ module VX_csr_data (
 	always @(posedge clk or posedge reset) begin
 		if (reset) begin
 			for (curr_e = 0; curr_e < 1024; curr_e=curr_e+1) begin
-				assign csr[curr_e] = 0;
+				csr[curr_e] <= 0;
 			end
 			cycle   <= 0;
 			instret <= 0;
@@ -79,4 +79,4 @@ module VX_csr_data (
    													read_instreth ? instret[63:32] : 
    															{{20{1'b0}}, csr[in_read_csr_address]};

-endmodule
+endmodule