From e76d05f7cef0da3c0b52f455caa4ad86c062be5b Mon Sep 17 00:00:00 2001
From: wgulian3 <wgulian@gatech.edu>
Date: Tue, 18 Feb 2020 13:24:18 -0500
Subject: [PATCH] Fix issues quartus synthesis issues

---
 rtl/VX_alu.v            | 10 +++++-----
 rtl/VX_csr_data.v       |  4 ++--
 rtl/VX_csr_pipe.v       |  3 ++-
 rtl/compat/VX_divide.v  |  4 ++--
 rtl/quartus/project.tcl |  1 +
 rtl/quartus/vortex.sdc  |  3 +++
 6 files changed, 15 insertions(+), 10 deletions(-)

diff --git a/rtl/VX_alu.v b/rtl/VX_alu.v
index 064651de..4a3caebe 100644
--- a/rtl/VX_alu.v
+++ b/rtl/VX_alu.v
@@ -28,8 +28,8 @@ module VX_alu(
             .PIPELINE(div_pipeline_len)
         ) unsigned_div (
             .clock(clk),
-            .aclr(0),
-            .clken(1), // TODO this could be disabled on inactive instructions
+            .aclr(1'b0),
+            .clken(1'b1), // TODO this could be disabled on inactive instructions
             .numer(ALU_in1),
             .denom(ALU_in2),
             .quotient(unsigned_div_result),
@@ -45,8 +45,8 @@ module VX_alu(
             .PIPELINE(div_pipeline_len)
         ) signed_div (
             .clock(clk),
-            .aclr(0),
-            .clken(1), // TODO this could be disabled on inactive instructions
+            .aclr(1'b0),
+            .clken(1'b1), // TODO this could be disabled on inactive instructions
             .numer(ALU_in1),
             .denom(ALU_in2),
             .quotient(signed_div_result),
@@ -209,4 +209,4 @@ module VX_alu(
 		end
 	`endif
 
-endmodule : VX_alu
\ No newline at end of file
+endmodule : VX_alu
diff --git a/rtl/VX_csr_data.v b/rtl/VX_csr_data.v
index ab62aa23..30382d2b 100644
--- a/rtl/VX_csr_data.v
+++ b/rtl/VX_csr_data.v
@@ -57,7 +57,7 @@ module VX_csr_data (
 	always @(posedge clk or posedge reset) begin
 		if (reset) begin
 			for (curr_e = 0; curr_e < 1024; curr_e=curr_e+1) begin
-				assign csr[curr_e] = 0;
+				csr[curr_e] <= 0;
 			end
 			cycle   <= 0;
 			instret <= 0;
@@ -79,4 +79,4 @@ module VX_csr_data (
     													read_instreth ? instret[63:32] : 
     															{{20{1'b0}}, csr[in_read_csr_address]};
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/rtl/VX_csr_pipe.v b/rtl/VX_csr_pipe.v
index a5727c60..f5abfc57 100644
--- a/rtl/VX_csr_pipe.v
+++ b/rtl/VX_csr_pipe.v
@@ -1,3 +1,4 @@
+`include "VX_define.v"
 
 module VX_csr_pipe (
 	input wire clk,    // Clock
@@ -102,4 +103,4 @@ module VX_csr_pipe (
 	assign VX_csr_wb.wb         = wb_s2;
 	assign VX_csr_wb.csr_result = final_csr_data;
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/rtl/compat/VX_divide.v b/rtl/compat/VX_divide.v
index 15d5871e..554f8a3f 100644
--- a/rtl/compat/VX_divide.v
+++ b/rtl/compat/VX_divide.v
@@ -49,7 +49,7 @@ module VX_divide
                 .numer(numer),
                 .denom(denom),
                 .quotient(quotient),
-                .remainder(remainder)
+                .remain(remainder)
             );
 
         end
@@ -135,4 +135,4 @@ module VX_divide
         end
     endgenerate
 
-endmodule : VX_divide
\ No newline at end of file
+endmodule : VX_divide
diff --git a/rtl/quartus/project.tcl b/rtl/quartus/project.tcl
index 204037be..ef2e86d8 100644
--- a/rtl/quartus/project.tcl
+++ b/rtl/quartus/project.tcl
@@ -70,6 +70,7 @@ set_global_assignment -name VERILOG_FILE ../shared_memory/VX_shared_memory_block
 set_global_assignment -name VERILOG_FILE ../shared_memory/VX_shared_memory.v
 set_global_assignment -name VERILOG_FILE ../shared_memory/VX_priority_encoder_sm.v
 set_global_assignment -name VERILOG_FILE ../shared_memory/VX_bank_valids.v
+set_global_assignment -name VERILOG_FILE ../compat/VX_divide.v
 set_global_assignment -name VERILOG_FILE ../VX_alu.v
 set_global_assignment -name VERILOG_FILE ../VX_back_end.v
 set_global_assignment -name VERILOG_FILE ../VX_context.v
diff --git a/rtl/quartus/vortex.sdc b/rtl/quartus/vortex.sdc
index 622e853d..b1fc92c0 100644
--- a/rtl/quartus/vortex.sdc
+++ b/rtl/quartus/vortex.sdc
@@ -4,3 +4,6 @@ create_clock -name {clk} -period "400 MHz" -waveform { 0.0 1.0 } [get_ports {clk
 
 derive_pll_clocks -create_base_clocks
 derive_clock_uncertainty
+
+
+