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using lzc instead of priority_encoder

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This commit is contained in:
Blaise Tine
2021-08-26 07:29:47 -07:00
parent 2a27bfbfd5
commit e494860f38
4 changed files with 30 additions and 36 deletions
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11
hw/rtl/VX_instr_demux.v
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@@ -26,13 +26,12 @@ module VX_instr_demux (
`endif `endif
wire gpu_req_ready; wire gpu_req_ready;
VX_priority_encoder #( VX_lzc #(
.N (`NUM_THREADS) .WIDTH (`NUM_THREADS)
) tid_select ( ) tid_select (
.data_in (ibuffer_if.tmask), .in_i (ibuffer_if.tmask),
.index (tid), .cnt_o (tid),
`UNUSED_PIN (onehot), `UNUSED_PIN (valid_o)
`UNUSED_PIN (valid_out)
); );
wire [31:0] next_PC = ibuffer_if.PC + 4; wire [31:0] next_PC = ibuffer_if.PC + 4;

18
hw/rtl/VX_warp_sched.v
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@@ -30,7 +30,7 @@ module VX_warp_sched #(
reg [`NUM_WARPS-1:0] stalled_warps; // asserted when a branch/gpgpu instructions are issued reg [`NUM_WARPS-1:0] stalled_warps; // asserted when a branch/gpgpu instructions are issued
reg [`NUM_WARPS-1:0][`NUM_THREADS-1:0] thread_masks; reg [`NUM_WARPS-1:0][`NUM_THREADS-1:0] thread_masks;
reg [`NUM_WARPS-1:0][31:0] warp_pcs, warp_next_pcs; reg [`NUM_WARPS-1:0][31:0] warp_pcs;
// barriers // barriers
reg [`NUM_BARRIERS-1:0][`NUM_WARPS-1:0] barrier_masks; // warps waiting on barrier reg [`NUM_BARRIERS-1:0][`NUM_WARPS-1:0] barrier_masks; // warps waiting on barrier
@@ -121,12 +121,11 @@ module VX_warp_sched #(
end end
if (ifetch_req_fire) begin if (ifetch_req_fire) begin
warp_next_pcs[ifetch_req_if.wid] <= ifetch_req_if.PC + 4; warp_pcs[ifetch_req_if.wid] <= ifetch_req_if.PC + 4;
end end
if (wstall_if.valid) begin if (wstall_if.valid) begin
stalled_warps[wstall_if.wid] <= wstall_if.stalled; stalled_warps[wstall_if.wid] <= wstall_if.stalled;
warp_pcs[wstall_if.wid] <= warp_next_pcs[wstall_if.wid];
end end
// join handling // join handling
@@ -200,13 +199,12 @@ module VX_warp_sched #(
wire [`NUM_WARPS-1:0] ready_warps = active_warps & ~(stalled_warps | barrier_stalls); wire [`NUM_WARPS-1:0] ready_warps = active_warps & ~(stalled_warps | barrier_stalls);
VX_priority_encoder #( VX_lzc #(
.N (`NUM_WARPS) .WIDTH (`NUM_WARPS)
) pri_enc ( ) wid_select (
.data_in (ready_warps), .in_i (ready_warps),
.index (schedule_wid), .cnt_o (schedule_wid),
.valid_out (schedule_valid), .valid_o (schedule_valid)
`UNUSED_PIN (onehot)
); );
wire [`NUM_WARPS-1:0][(`NUM_THREADS + 32)-1:0] schedule_data; wire [`NUM_WARPS-1:0][(`NUM_THREADS + 32)-1:0] schedule_data;

26
hw/rtl/cache/VX_miss_resrv.v vendored
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@@ -102,22 +102,20 @@ module VX_miss_resrv #(
end end
end end
VX_priority_encoder #( VX_lzc #(
.N (MSHR_SIZE) .WIDTH (MSHR_SIZE)
) dequeue_pe ( ) dequeue_sel (
.data_in (valid_table_x & ready_table_x), .in_i (valid_table_x & ready_table_x),
.index (dequeue_id_x), .cnt_o (dequeue_id_x),
.valid_out (dequeue_val_x), .valid_o (dequeue_val_x)
`UNUSED_PIN (onehot)
); );
VX_priority_encoder #( VX_lzc #(
.N (MSHR_SIZE) .WIDTH (MSHR_SIZE)
) allocate_pe ( ) allocate_sel (
.data_in (~valid_table_n), .in_i (~valid_table_n),
.index (allocate_id_n), .cnt_o (allocate_id_n),
.valid_out (allocate_rdy_n), .valid_o (allocate_rdy_n)
`UNUSED_PIN (onehot)
); );
always @(*) begin always @(*) begin

11
hw/rtl/libs/VX_index_buffer.v
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@@ -29,13 +29,12 @@ module VX_index_buffer #(
wire free_valid; wire free_valid;
wire [ADDRW-1:0] free_index; wire [ADDRW-1:0] free_index;
VX_priority_encoder #( VX_lzc #(
.N (SIZE) .WIDTH (SIZE)
) free_slots_encoder ( ) free_slots_encoder (
.data_in (free_slots_n), .in_i (free_slots_n),
.index (free_index), .cnt_o (free_index),
`UNUSED_PIN (onehot), .valid_o (free_valid)
.valid_out (free_valid)
); );
always @(*) begin always @(*) begin