diff --git a/hw/rtl/VX_instr_demux.v b/hw/rtl/VX_instr_demux.v
index 1fd79f37..e497bfcb 100644
--- a/hw/rtl/VX_instr_demux.v
+++ b/hw/rtl/VX_instr_demux.v
@@ -26,13 +26,12 @@ module VX_instr_demux (
 `endif
     wire gpu_req_ready;
 
-    VX_priority_encoder #(
-        .N (`NUM_THREADS)
+    VX_lzc #(
+        .WIDTH (`NUM_THREADS)
     ) tid_select (
-        .data_in    (ibuffer_if.tmask),
-        .index      (tid),
-        `UNUSED_PIN (onehot),
-        `UNUSED_PIN (valid_out)
+        .in_i       (ibuffer_if.tmask),
+        .cnt_o      (tid),
+        `UNUSED_PIN (valid_o)
     );
 
     wire [31:0] next_PC = ibuffer_if.PC + 4;
diff --git a/hw/rtl/VX_warp_sched.v b/hw/rtl/VX_warp_sched.v
index 89673310..f6bff82f 100644
--- a/hw/rtl/VX_warp_sched.v
+++ b/hw/rtl/VX_warp_sched.v
@@ -30,7 +30,7 @@ module VX_warp_sched #(
     reg [`NUM_WARPS-1:0] stalled_warps;  // asserted when a branch/gpgpu instructions are issued
     
     reg [`NUM_WARPS-1:0][`NUM_THREADS-1:0] thread_masks;
-    reg [`NUM_WARPS-1:0][31:0] warp_pcs, warp_next_pcs;
+    reg [`NUM_WARPS-1:0][31:0] warp_pcs;
 
     // barriers
     reg [`NUM_BARRIERS-1:0][`NUM_WARPS-1:0] barrier_masks; // warps waiting on barrier
@@ -121,12 +121,11 @@ module VX_warp_sched #(
             end
 
             if (ifetch_req_fire) begin
-                warp_next_pcs[ifetch_req_if.wid] <= ifetch_req_if.PC + 4;
+                warp_pcs[ifetch_req_if.wid] <= ifetch_req_if.PC + 4;
             end
 
             if (wstall_if.valid) begin
                 stalled_warps[wstall_if.wid] <= wstall_if.stalled;
-                warp_pcs[wstall_if.wid] <= warp_next_pcs[wstall_if.wid];
             end
 
             // join handling
@@ -200,13 +199,12 @@ module VX_warp_sched #(
 
     wire [`NUM_WARPS-1:0] ready_warps = active_warps & ~(stalled_warps | barrier_stalls);
 
-    VX_priority_encoder #(
-        .N (`NUM_WARPS)
-    ) pri_enc (
-        .data_in    (ready_warps),
-        .index      (schedule_wid),
-        .valid_out  (schedule_valid),
-        `UNUSED_PIN (onehot)
+    VX_lzc #(
+        .WIDTH (`NUM_WARPS)
+    ) wid_select (
+        .in_i    (ready_warps),
+        .cnt_o   (schedule_wid),
+        .valid_o (schedule_valid)
     );
 
     wire [`NUM_WARPS-1:0][(`NUM_THREADS + 32)-1:0] schedule_data;
diff --git a/hw/rtl/cache/VX_miss_resrv.v b/hw/rtl/cache/VX_miss_resrv.v
index 1fab4a63..46802a70 100644
--- a/hw/rtl/cache/VX_miss_resrv.v
+++ b/hw/rtl/cache/VX_miss_resrv.v
@@ -102,22 +102,20 @@ module VX_miss_resrv #(
         end
     end
 
-    VX_priority_encoder #(
-        .N (MSHR_SIZE)
-    ) dequeue_pe (
-        .data_in    (valid_table_x & ready_table_x),
-        .index      (dequeue_id_x),
-        .valid_out  (dequeue_val_x),
-        `UNUSED_PIN (onehot)    
+    VX_lzc #(
+        .WIDTH (MSHR_SIZE)
+    ) dequeue_sel (
+        .in_i    (valid_table_x & ready_table_x),
+        .cnt_o   (dequeue_id_x),
+        .valid_o (dequeue_val_x)
     );
 
-    VX_priority_encoder #(
-        .N (MSHR_SIZE)
-    ) allocate_pe (
-        .data_in    (~valid_table_n),
-        .index      (allocate_id_n),
-        .valid_out  (allocate_rdy_n),
-        `UNUSED_PIN (onehot)    
+    VX_lzc #(
+        .WIDTH (MSHR_SIZE)
+    ) allocate_sel (
+        .in_i    (~valid_table_n),
+        .cnt_o   (allocate_id_n),
+        .valid_o (allocate_rdy_n)
     );
 
     always @(*) begin
diff --git a/hw/rtl/libs/VX_index_buffer.v b/hw/rtl/libs/VX_index_buffer.v
index 8a9e7607..689485a5 100644
--- a/hw/rtl/libs/VX_index_buffer.v
+++ b/hw/rtl/libs/VX_index_buffer.v
@@ -29,13 +29,12 @@ module VX_index_buffer #(
     wire free_valid;
     wire [ADDRW-1:0] free_index;
 
-    VX_priority_encoder #(
-        .N (SIZE)
+    VX_lzc #(
+        .WIDTH (SIZE)
     ) free_slots_encoder (
-        .data_in    (free_slots_n),
-        .index      (free_index),  
-        `UNUSED_PIN (onehot),
-        .valid_out  (free_valid)
+        .in_i    (free_slots_n),
+        .cnt_o   (free_index),
+        .valid_o (free_valid)
     );  
 
     always @(*) begin