wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

minor update

Browse Source
This commit is contained in:
Blaise Tine
2021-04-03 04:24:37 -07:00
parent f829bd3c18
commit d6552a8851
1 changed files with 4 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
hw/rtl/cache/VX_cache_core_rsp_merge.v vendored
View File

@@ -98,7 +98,8 @@ module VX_cache_core_rsp_merge #(
wire core_rsp_valid_any = (| per_bank_core_rsp_valid); wire core_rsp_valid_any = (| per_bank_core_rsp_valid);
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (NUM_REQS + CORE_TAG_WIDTH + (NUM_REQS *`WORD_WIDTH)) .DATAW (NUM_REQS + CORE_TAG_WIDTH + (NUM_REQS *`WORD_WIDTH)),
.BUFFERED (1)
) pipe_reg ( ) pipe_reg (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
@@ -146,7 +147,8 @@ module VX_cache_core_rsp_merge #(
for (genvar i = 0; i < NUM_REQS; i++) begin for (genvar i = 0; i < NUM_REQS; i++) begin
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (CORE_TAG_WIDTH + `WORD_WIDTH) .DATAW (CORE_TAG_WIDTH + `WORD_WIDTH),
.BUFFERED (1)
) pipe_reg ( ) pipe_reg (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),