From d6552a8851b904b041b8fd151a811e8b09c0fa38 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Sat, 3 Apr 2021 04:24:37 -0700 Subject: [PATCH] minor update --- hw/rtl/cache/VX_cache_core_rsp_merge.v | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/rtl/cache/VX_cache_core_rsp_merge.v b/hw/rtl/cache/VX_cache_core_rsp_merge.v index dad89c15..4bed779d 100644 --- a/hw/rtl/cache/VX_cache_core_rsp_merge.v +++ b/hw/rtl/cache/VX_cache_core_rsp_merge.v @@ -98,7 +98,8 @@ module VX_cache_core_rsp_merge #( wire core_rsp_valid_any = (| per_bank_core_rsp_valid); VX_skid_buffer #( - .DATAW (NUM_REQS + CORE_TAG_WIDTH + (NUM_REQS *`WORD_WIDTH)) + .DATAW (NUM_REQS + CORE_TAG_WIDTH + (NUM_REQS *`WORD_WIDTH)), + .BUFFERED (1) ) pipe_reg ( .clk (clk), .reset (reset), @@ -146,7 +147,8 @@ module VX_cache_core_rsp_merge #( for (genvar i = 0; i < NUM_REQS; i++) begin VX_skid_buffer #( - .DATAW (CORE_TAG_WIDTH + `WORD_WIDTH) + .DATAW (CORE_TAG_WIDTH + `WORD_WIDTH), + .BUFFERED (1) ) pipe_reg ( .clk (clk), .reset (reset),